Issue No.10 - October (2003 vol.52)
David H. Albonesi , IEEE
Sandhya Dwarkadas , IEEE
<p><b>Abstract</b>—The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per-application phase basis using a novel configuration management algorithm. In comparison to a conventional design that is fixed at a single design point targeted to the average application, the <it>dynamically tunable</it> cache and TLB hierarchy can be tailored to the needs of each application phase. The configuration algorithm dynamically detects phase changes and selects a configuration based on the application's ability to tolerate different hit and miss latencies in order to improve the memory energy-delay product. We evaluate the performance and energy consumption of our approach and project the effects of technology scaling trends on our design.</p>
High performance microprocessors, memory hierarchy, reconfigurable architectures, energy and performance of on-chip caches.
David H. Albonesi, Rajeev Balasubramonian, Sandhya Dwarkadas, "A Dynamically Tunable Memory Hierarchy", IEEE Transactions on Computers, vol.52, no. 10, pp. 1243-1258, October 2003, doi:10.1109/TC.2003.1234523