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Generalized Earliest-First Fast Addition Algorithm
October 2003 (vol. 52 no. 10)
pp. 1233-1242

Abstract—This paper presents a generalized earliest-first (GEF) addition algorithm to accelerate carry propagation addition (CPA). A set of operators and notations have been developed to describe and analyze traditional carry-lookahead or conditional-sum-based algorithms. The proposed GEF algorithm schedules bit-level operations of CPA in an earliest-first manner to reduce the overall latency. With the aid of the developed operators and notations, the algorithm can be generalized to any algorithm based on carry-lookahead or conditional-sum rule. An adder generated by using the GEF algorithm outperforms traditional algorithms when inputs do not arrive simultaneously.

[1] J. Sklansky, Conditional Sum Addition Logic IRE Trans. Electronic Computers, vol. 9, no. 2 pp. 226-231, June 1960.
[2] K. Hwang, Computer Arithmetic: Principles, Architecture, and Design p. 81. John Wiley&Sons, 1976.
[3] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, second ed. pp. 526-536, Addison Wesley, 1993.
[4] K.-H Cheng, S.-M. Chiang, and S.-W. Cheng, The Improvement of Conditional Sum Adder for Low Power Applications Proc. 11th Ann. IEEE Int'l Application Specific Integrated Circuits Conf., pp. 131-134, 1998.
[5] P. Kelliher, R.M. Owens, M.J. Irwin, and T.-T. Hwang, ELM A Fast Addition Algorithm Discovered by a Program IEEE Trans. Computers, vol. 41, no. 9, Sept. 1992.
[6] H. Lindkvist and P. Andersson, Techniques for Fast CMOS-Based Conditional Sum Adders Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 626-635, Oct. 1994.
[7] H. Kunz and R. Zimmermann, High-Performance Adder Circuit Generators in Parameterized Structural VHDL Technical Report No. 96/7, Integrated Systems Laboratory, ETH Zurich Aug. 1996.
[8] M.D. Ercegovac et al., Fast Multiplication without Carry-Propagate Addition , IEEE Trans. Computers, vol. 39, no. 11, Nov. 1990.
[9] R.K. Kolagotla et al., VLSI Implementation of a 200-Mhz 16$\times$16 Left-to-Right Carry-Free Multiplier in 0.35$\mu \rm m$CMOS Technology for Next-Generation DSPs , Proc. IEEE 1997 Custom Integrated Circuits Conf., pp. 469-472, 1997.
[10] P.F. Stelling and V.G. Oklobdzija, Optimal Designs for Multipliers and Multiply-Accumulators Proc. 15th IMACS World Congress on Scientific Computation, Modeling, and Applied Mathematics, vol. 4, pp. 739-744, Aug. 1997.
[11] W.-C. Yeh and C.-W. Jen, A High-Speed Booth Encoded Parallel Multiplier Design IEEE Trans. Computers, vol. 49, no. 7, pp. 692-701, July 2000.
[12] C.N. Nagendra, M.J. Irwin, and R.M. Owens, Area-Time-Power Tradeoffs in Parallel Adders IEEE Trans. Circuits and Systems XII: Analog and Digital Signal Processing, vol. 43, no. 10, Oct. 1996.
[13] W.-C. Yeh and C.-W. Jen, On the Study of Logarithmic Time Parallel Adders Proc. IEEE Workshop Signal Processing Systems, pp. 459-466, 2000.
[14] R.P. Brent and H.-T. Kung, A Regular Layout for Parallel Adders IEEE Trans. Computers, vol. 31, no. 3, Mar. 1982.
[15] Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corp., Mar. 1998.

Index Terms:
Carry-propagation adder, final adder, carry-lookahead, conditional-sum.
Citation:
Wen-Chang Yeh, Chein-Wei Jen, "Generalized Earliest-First Fast Addition Algorithm," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1233-1242, Oct. 2003, doi:10.1109/TC.2003.1234522
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