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VLSI Implementation of a Low-Power Antilogarithmic Converter
September 2003 (vol. 52 no. 9)
pp. 1221-1228

Abstract—This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 \mum CMOS technology, and its combinational logic implementation requires 1,500\lambda\times2,800\lambda of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 milliwatts.

[1] J.N. Mitchell Jr., Computer Multiplication and Division Using Binary Logarithms IRE Trans. Electronic Computers, vol. 11, pp. 512-517, Aug. 1962.
[2] E.L. Hall, D.D. Lynch, and S.J. Dwyer III, Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications IEEE Trans. Computers, vol. 19, pp. 97-105, Feb. 1970.
[3] J.M. Muller, Elementary Functions. Algorithms and Implementation. Birkhauser, 1997.
[4] M.J. Schulte and E.E. Swartzlander Jr., Hardware Designs for Exactly Rounded Elementary Functions IEEE Trans. Computers, vol. 43, no. 8, pp. 964-973, Aug. 1994.
[5] M.J. Schulte and J.E. Stine, “Symmetric Bipartite Tables for Accurate Function Approximation” Proc. 13th Symp. Computer Arithmetic (ARITH13), pp. 175-183, 1997.
[6] M.J. Arnold and C. Walter, Unrestricted Faithful Rounding Is Good Enough for Some LNS Applications Proc. 15th IEEE Symp. Computer Arithmetic, pp. 237-246, June 2001.
[7] V. Paliouras and T. Stouraitis, Low-Power Properties of the Logarithmic Number System Proc. 15th IEEE Symp. Computer Arithmetic, pp. 229-236, June 2001.
[8] K.H. Abed and R.E. Siferd, CMOS VLSI Implementation of 16-Bit Logarithm and Anti-Logarithm Converters Proc. IEEE Midwest Symp. Circuits and Systems, pp. 776-779, Aug. 1999.
[9] K.H. Abed and R.E. Siferd, CMOS VLSI Implementation of a 32-Bit Logarithmic Converter IEEE Trans. Computers, submitted.
[10] S.W. Smith, The Scientist and Engineer's Guide to Digital Signal Processing. San Diego, Calif.: California Publishing, 1997.

Index Terms:
Antilogarithm, binary logarithm, leading-one detector, logarithmic number system (LNS), logarithmic shifter, low-power circuits.
Khalid H. Abed, Raymond E. Siferd, "VLSI Implementation of a Low-Power Antilogarithmic Converter," IEEE Transactions on Computers, vol. 52, no. 9, pp. 1221-1228, Sept. 2003, doi:10.1109/TC.2003.1228517
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