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Issue No.09 - September (2003 vol.52)
pp: 1221-1228
<p><b>Abstract</b>—This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 <tmath>\mu</tmath>m CMOS technology, and its combinational logic implementation requires <tmath>1,500\lambda\times2,800\lambda</tmath> of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 milliwatts.</p>
Antilogarithm, binary logarithm, leading-one detector, logarithmic number system (LNS), logarithmic shifter, low-power circuits.
Khalid H. Abed, Raymond E. Siferd, "VLSI Implementation of a Low-Power Antilogarithmic Converter", IEEE Transactions on Computers, vol.52, no. 9, pp. 1221-1228, September 2003, doi:10.1109/TC.2003.1228517
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