This Article 
 Bibliographic References 
 Add to: 
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
September 2003 (vol. 52 no. 9)
pp. 1215-1221

Abstract—This paper presents a scalable architecture for the computation of modular multiplication, based on the Montgomery multiplication (MM) algorithm. A word-based version of MM is presented and used to explain the main concepts in the hardware design. The proposed multiplier is able to work with any precision of the input operands, limited only by memory or control constraints. Its architecture gives enough freedom to select the word size and the degree of parallelism to be used, according to the available area and/or desired performance. Design trade offs are analyzed in order to identify adequate hardware configurations for a given area or bandwidth requirement.

[1] P.L. Montgomery, Modular Multiplication without Trial Division Math. of Computation, vol. 44, no. 170, pp. 519-521, Apr., 1985.
[2] H. Orup, “Simplifying Quotient Determination in High-Radix Modular Multiplication,” Proc. 12th Symp. Computer Arithmetic, pp. 193-199, 1995.
[3] C.K. Koc, T. Acar, and B. Kaliski, “Analyzing and Comparing Montgomery Multiplication Algorithms,” IEEE Micro, vol. 16, no. 3, pp. 26-33, June 1996.
[4] A. Bernal and A. Guyot, Design of a Modular Multiplier Based on Montgomery's Algorithm Proc. 13th Int'l Conf. Design of Circuits and Integrated Systems (DCIS '98), Nov. 1998.
[5] C.-C. Yang, T.-S. Chang, and C.-W. Jen, A New RSA Cryptosystem Hardware Design Based on Montgomery's Algorithm IEEE Trans. on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 45, no. 7, pp. 908-913, July 1998.
[6] C.-Y. Su, S.-A. Hwang, P.-S. Chen, and C.-W. Wu, An Improved Montgomery's Algorithm for High-Speed RSA Public-Key Cryptosystem IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 7, no. 2, pp. 280-284, June 1999.
[7] S.E. Eldridge and C.D. Walter, “Hardware Implementation of Montgomery's Modular Multiplication Algorithm,” IEEE Trans. Computers, vol. 42, no. 7, pp. 693-699, July 1993.
[8] P. Kornerup, "High-Radix Modular Multiplication for Cryptosystems," Proc. 11th IEEE Symp. Computer Arithmetic, G. Jullien, M.J Irwin, and E. Swartzlander, eds., pp. 277-283,Windsor, Canada, 1993.
[9] C.D. Walter, "Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition," IEEE Trans. Computers, vol. 46, no. 2, pp. 139-141, Feb. 1997.
[10] A. Royo, J. Moran, and J.C. Lopez, Design and Implementation of a Coprocessor for Cryptography Applications Proc. European Design and Test Conf., pp. 213-217, Mar. 1997.
[11] T. Hamano, N. Takagi, S. Yajima, and F.P. Preparata, O(n)-Depth Circuit Algorithm for Modular Exponentiation Proc. 12th IEEE Symp. Computer Arithmetic, S. Knowles and W.H. McAllister, eds., pp. 188-192, July 1995.
[12] ÇK. Koç and T. Acar, “Fast Software Exponentiation in${\rm GF}(2^k)$,” Proc. 13th Symp. Computer Arithmetic, pp. 279-287, July 1997.
[13] W. Diffie and M.E. Hellman, New Directions in Cryptography IEEE Trans. Information Theory, vol. 22, pp. 644-654, 1976.
[14] R.L. Rivest,A. Shamir, and L.A. Adleman,"A Method for Obtaining Digital Signatures and Public Key Cryptosystems," Comm. ACM, vol. 21, pp. 120-126, 1978.
[15] A.J. Menezes, Elliptic Curve Public Key Cryptosystems. Boston: Kluwer Academic Publishers, 1993.
[16] Ç.K. Koç and T. Acar, “Montgomery Multplication in$\big. GF(2^k)\bigr.$,” Design, Codes, and Cryptography, vol. 14, no. 1, pp. 57-69, 1998.
[17] T. Blum and C. Paar, “Montgomery Modular Exponentiation on Reconfigurable Hardware,” Proc. 14th Symp. Computer Arithmetic, pp. 70-77, 1999.
[18] C.D. Walter, “Systolic Modular Multiplier,” IEEE Trans. Computers, vol. 42, no. 3, pp. 376-378, Mar. 1993.
[19] D.I. Moldovan and J.A.B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays,” IEEE Trans. Computers, vol. 35, no. 1, pp.1-12, Jan. 1986.
[20] A.F. Tenca and Ç.K. Koç, A Scalable Architecture for Montgomery Multiplication Proc. First Int'l Workshop Cryptographic Hardware and Embedded Systems CHES '99, Ç.K. Koçand C. Paar, eds., pp. 94-108, Aug. 1999.
[21] G. Todorov, ASIC Design, Implementation, and Analysis of a Scalable High-Radix Montgomery Multiplier MS thesis, Oregon State Univ., Dec. 2000.
[22] A.F. Tenca, G. Todorov, and Ç.K. Koç, High-Radix Design of a Scalable Modular Multiplier Proc. Workshop Cryptographic Hardware and Embedded Systems, Ç.K. Koç, D. Naccache, and C. Paar, eds., pp. 185-201, 2001.
[23] C. Hachez and J.-J. Quisquater, “Montgomery Exponentiation with No Final Subtractions: Improved Results,” Proc. Cryptographic Hardware and Embedded Systems—CHES 2000, pp. 293-301, 2000.
[24] T. Yanik, E. Savas, and Ç.K. Koç, Incomplete Reduction in Modular Arithmetic IEE Proc.-Computers and Digital Techniques, vol. 149, no. 2, pp. 46-52, Mar. 2002.
[25] A.F. Tenca, Variable Long-Precision Arithmetic (VLPA) for Reconfigurable Coprocessor Architectures PhD thesis, Univ. California Los Angeles, 1998.
[26] B. Kurniawan, ASIC Design and Implementation of a Parallel Exponentiation Algorithm Using Optimized Scalable Montgomery Multipliers MS thesis, Oregon State Univ., Corvallis, 2002.
[27] E. Savas, A.F. Tenca, and Ç.K. Koç, “A Scalable and Unified Multiplier Architecture for Finite Fields$\big. GF(p)\bigr.$and$\big. GF(2^m)\bigr.$,” Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), Ç.K. Koçand C. Paar, eds., pp. 277-292, 2000.

Index Terms:
Cryptography, Montgomery multiplication, modular multiplication, modular multiplier, scalable multiplier.
Alexandre F. Tenca, ?etin K. Ko?, "A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm," IEEE Transactions on Computers, vol. 52, no. 9, pp. 1215-1221, Sept. 2003, doi:10.1109/TC.2003.1228516
Usage of this product signifies your acceptance of the Terms of Use.