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Cache Coherence in Intelligent Memory Systems
July 2003 (vol. 52 no. 7)
pp. 960-966

Abstract—The Active Pages model of intelligent memory can speed up data-intensive applications by up to two to three orders of magnitude over conventional systems. A fundamental problem with intelligent memory, however, arises when data cached by the processor is modified by logic in the memory. The Active Page model inherently limits sharing, keeping coherence tractable, but exacerbates saturation problems. We first present a hybrid snoopy/directory protocol for use in Active Pages. Limited sharing allows for a low-latency, low-bandwidth hybrid protocol. A transparent remapping mechanism is added for efficient caching. On smaller data sizes, explicit flushing and hardware coherence exhibit similar performance, but hardware coherence is easier to program and uses less bandwidth. Finally, we examine SMP multiprocessor systems to mitigate saturation effects. As the number of threads increases, the bandwidth needs increase, making hardware coherence even more attractive.

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Index Terms:
Intelligent memory, merged DRAM logic, cache coherence.
Citation:
Diana Keen, Mark Oskin, Justin Hensley, Frederic T. Chong, "Cache Coherence in Intelligent Memory Systems," IEEE Transactions on Computers, vol. 52, no. 7, pp. 960-966, July 2003, doi:10.1109/TC.2003.1214343
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