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Deterministic BIST for RNS Adders
July 2003 (vol. 52 no. 7)
pp. 896-906

Abstract—Modulo 2^n - 1 adders as fast as n{\hbox{-}}{\rm bit} 2's complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2^n , 2^n - 1, and any other of the form 2^k - 1, with k, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2^n ,2^n - 1,2^k - 1,2^l - 1,\ldots, with l. The derived test set is reusable; it can be used for any value of n, k, l,\ldots, regardless of the implementation library used and is composed of n^2 + 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n^2 + 2n cycles. Static CMOS implementations reveal that the proposed BIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.

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Index Terms:
Residue Number System, Built-In Self-Test, deterministic and pseudorandom tests, formal test sets.
Citation:
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou, "Deterministic BIST for RNS Adders," IEEE Transactions on Computers, vol. 52, no. 7, pp. 896-906, July 2003, doi:10.1109/TC.2003.1214338
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