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Variable Instruction Set Architecture and Its Compiler Support
July 2003 (vol. 52 no. 7)
pp. 881-895

Abstract—A variable instruction set processor provides a dictionary that enables the compiler to configure the best instruction set to use for executing the program being compiled. This paper describes Cognigine's variable instruction set communication architecture (VISC Architecture) and the implementation of a compiler that provides effective compilation and optimization support for this target. The compiler implementation involves the use of an abstract operation representation that enables the code generator to optimize toward the core architecture of the processor without committing to any specific instruction format. It then uses an enumeration approach to instruction scheduling that determines the final forms of the instructions to be generated while still adhering to the irregular constraints imposed by the architecture. The enumeration approach also allows the incorporation of dictionary reuse functionality to provide trade offs between program performance and dictionary budget. Finally, we provide experimental results to show the effectiveness of these compilation techniques in supporting Cognigine's VISC Architecture.

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Index Terms:
Configurable code generation, dictionary, embedded processor, enumeration, instruction scheduling, program representation, resource modeling, variable instruction set.
Jack Liu, Fred Chow, Timothy Kong, Rupan Roy, "Variable Instruction Set Architecture and Its Compiler Support," IEEE Transactions on Computers, vol. 52, no. 7, pp. 881-895, July 2003, doi:10.1109/TC.2003.1214337
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