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Issue No.07 - July (2003 vol.52)
pp: 862-880
ABSTRACT
<p><b>Abstract</b>—While the desire to use commodity parts in the communication architecture of a DSM multiprocessor offers advantages in cost and design time, the impact on application performance is unclear. We study this performance impact through detailed simulation, analytical modeling, and experiments on a flexible DSM prototype, using a range of parallel applications. We adapt the logP model to characterize the communication architectures of DSM machines. The <tmath>l</tmath> (network latency) and <tmath>o</tmath> (controller occupancy) parameters are the keys to performance in these machines, with the <tmath>g</tmath> (node-to-network bandwidth) parameter becoming important only for the fastest controllers. We show that, of all the logP parameters, controller occupancy has the greatest impact on application performance. Of the two contributions of occupancy to performance degradation—the latency it adds and the contention it induces—it is the contention component that governs performance regardless of network latency, showing a quadratic dependence on <tmath>o</tmath>. As expected, techniques to reduce the impact of latency make controller occupancy a greater bottleneck. Surprisingly, the performance impact of occupancy is substantial, even for highly-tuned applications and even in the absence of latency hiding techniques. Scaling the problem size is often used as a technique to overcome limitations in communication latency and bandwidth. Through experiments on a DSM prototype, we show that there are important classes of applications for which the performance lost by using higher occupancy controllers cannot be regained easily, if at all, by scaling the problem size.</p>
INDEX TERMS
Occupancy, distributed shared memory multiprocessors, communication controller, latency, bandwidth, queuing model, flexible node controller.
CITATION
Mark Heinrich, Chris Holt, Jaswinder Pal Singh, Edward Rothberg, Mainak Chaudhuri, "Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation", IEEE Transactions on Computers, vol.52, no. 7, pp. 862-880, July 2003, doi:10.1109/TC.2003.1214336
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