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A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes
July 2003 (vol. 52 no. 7)
pp. 835-847

Abstract—Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting—Single b-bit byte Error Detecting (St/bEC-SbED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b=8, the S3/8 EC-S8ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S3/8 EC-S8ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S(b-1)/bEC-SbED codes, i.e., perfect St/bEC-SbED codes for the case where t=b-1, do exist and provides a theorem to construct these codes.

[1] T.J. O'Gorman, J.M. Ross, A.H. Taber, et al., Field Testing for Cosmic Ray Soft Errors in Semiconductor Memories , IBM J. Research and Development, vol. 40, no. 1, pp. 41-50, Jan. 1996.
[2] L.W. Massengil, Cosmic and Terrestrial Single Event Radian Effects in Dynamic Random Access Memories IEEE Trans. Nuclear Science, vol. 43, no. 2, pp. 576-593, Apr. 1996.
[3] G. Umanesan and E. Fujiwara, A Class of Random Multiple Bits in a Byte Error Correcting (${\rm{S}}_{t/b}{\rm{EC}}$) Codes for Semiconductor Memory Systems Proc. 2002 Pacific Rim Int'l Symp. Dependable Computing, Dec. 2002.
[4] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[5] K. Numata, Y. Oowaki, Y. Itoh, et al., New Nibbled-Page Architecture for High-Density DRAM's IEEE J. Solid State Circuits, vol. 24, no. 4, pp. 900-904, Aug. 1989.
[6] T. Saeki, Y. Nakaoka, M. Fujita, et al., A 2.5-ns Clock Access, 256mhz, 256mb SDRAM with Synchronous Mirror Delay IEEE J. Solid State Circuits, vol. 31, no. 11, pp. 1656-1668, Nov. 1996.
[7] T. Sunaga, K. Hosokawa, Y. Nakamura, et al., A Full Bit Perfect Architecture for Synchronous DRAM's IEEE J. Solid State Circuits, vol. 30, no. 9, pp. 998-1005, Nov. 1995.
[8] S. Kaneda, A General Class of Odd-Weight-Column${\rm{SEC{\hbox{-}}DED{\hbox{-}}S}}_{b}{\rm{ED}}$Codes for Memory System Applications IEEE Trans. Computers, vol. 33, no. 8, pp. 737-739, Aug. 1984.
[9] G. Umanesan, and E. Fujiwara, Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems IEICE Trans. Fundamentals, vol. E85-A, no. 2, pp. 490-496, Feb. 2002.
[10] W. Peterson, Jr. and E.J. Weldon, Error-Correcting Codes. MIT Press, 1972.
[11] A.A. Davydov and A.Y. Drozhzhina-Labinskaya, Length 4 Byte Error and Double Independent Error Correction by BCH Code in Semiconductor Memories Automation and Remote Control, vol. 50, no. 11, pp. 1570-1579, Nov. 1989.
[12] N.H. Vaidya and D.K. Pradhan, A New Class of Bit and Byte Error Control Codes IEEE Trans. Information Theory, vol. 38, no. 5, pp. 1617-1623, Sept. 1992.
[13] G. Umanesan and E. Fujiwara, Random Double Bit Error Correcting Single$b{\hbox{-}}{\rm{Bit}}$Byte Error Correcting (${\rm{DEC{\hbox{-}}S}}_{b}{\rm{EC}}$) Codes for Memory Systems IEICE Trans. Fundamentals, vol. E85-A, no. 1, pp. 273-276, Jan. 2002.
[14] S.J. Hong and A.M. Patel, A General Class of Maximal Codes for Computer Applications IEEE Trans. Computers, vol. 21, no. 12, pp. 1322-1331, Dec. 1972.
[15] G. Umanesan and E. Fujiwara, Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems IEICE Trans. Fundamentals, vol. E85-A, no. 2, pp. 513-517, Feb. 2002.
[16] Y. Joji and E. Fujiwara, A Class of Byte Error Control Codes Based on Hierarchical Error Model Technical Report of IEICE, FTS96-58, Feb. 1997.

Index Terms:
Random multiple bits in a byte error, single t/b-error correcting—single b-bit byte error detecting (St/bEC-SbED) codes.
Citation:
Ganesan Umanesan, Eiji Fujiwara, "A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes," IEEE Transactions on Computers, vol. 52, no. 7, pp. 835-847, July 2003, doi:10.1109/TC.2003.1214333
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