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An Intelligent Cache System with Hardware Prefetching for High Performance
May 2003 (vol. 52 no. 5)
pp. 607-616

Abstract—In this paper, we present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. The proposed cache, which we call a Selective-Mode Intelligent (SMI) cache, consists of three parts: a direct-mapped cache with a small block size, a fully associative spatial buffer with a large block size, and a hardware prefetching unit. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer for a time period. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. The overhead of this prefetching operation is shown to be negligible. We also show that the prefetch operation is highly accurate: Over 90 percent of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance. Also, the SMI cache can reduce the miss ratio by around 20 percent and the average memory access time by 10 percent, compared with a victim-buffer cache configuration.

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Index Terms:
Memory hierarchy, dual data cache, temporal locality, spatial locality, prefetching.
Citation:
Jung-Hoon Lee, Seh-woong Jeong, Shin-Dug Kim, Charles Weems, "An Intelligent Cache System with Hardware Prefetching for High Performance," IEEE Transactions on Computers, vol. 52, no. 5, pp. 607-616, May 2003, doi:10.1109/TC.2003.1197127
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