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Issue No.04 - April (2003 vol.52)
pp: 483-491
ABSTRACT
<p><b>Abstract</b>—This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semi-custom design flows. Contrary to other publications, a complete architecture (even including CBC mode) that is scalable in terms of throughput and in terms of the used key size is described. Similarities of encryption and decryption are utilized to provide a high level of performance using only a relatively small area (10,799 gate equivalents for the standard configuration). This performance is reached by balancing the combinational paths of the design. No other published AES hardware architecture provides similar balancing or a comparable regularity. Implementations of the fastest configuration of the architecture provide a throughput of 241 Mbits/sec on a 0.6 <tmath>\mu</tmath>m CMOS process using standard cells.</p>
INDEX TERMS
Advanced Encryption Standard (AES), hardware architecture, IP module, VLSI, scalability, regularity.
CITATION
Stefan Mangard, Manfred Aigner, Sandra Dominikus, "A Highly Regular and Scalable AES Hardware Architecture", IEEE Transactions on Computers, vol.52, no. 4, pp. 483-491, April 2003, doi:10.1109/TC.2003.1190589
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