This Article 
 Bibliographic References 
 Add to: 
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
March 2003 (vol. 52 no. 3)
pp. 293-309

Abstract—Spot defects in memory devices are caused by imperfections in the fabrication process of these devices. In order to analyze the faulty effect of spot defects on the memory behavior, simulations have been performed on an electrical model of the memory in which the defects are injected, causing opens, shorts, or bridges. In this paper, simulation is used to analyze the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of most traditional memory fault models and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for eDRAMs. Conditions to test the newly established fault models, together with a test, are also given.

[1] S. Iyer and H. Kalter, "Embedded DRAM Technology: Opportunities and Challenges," IEEE Spectrum, Apr. 1999, pp. 56-64.
[2] A. Van de Goor, Testing Semiconductor Memories, John Wiley&Sons, New York, 1991.
[3] R.D. Adams and E.S. Cooley, “Analysis of a Deceptive Destructive Read Memory Fault Model and Recommended Testing,” Proc. IEEE North Atlantic Test Workshop, 1996.
[4] A.J. van de Goor and J. de Neef, “Industrial Evaluation of DRAM Tests,” Proc. Design, Automation, and Test in Europe, pp. 623-630, 1999.
[5] I. Schanstra and A.J. van de Goor, “Industrial Evaluation of Stress Combinations for March Tests Applied to SRAMs,” Proc. IEEE Int'l Test Conf., pp. 983-992, 1999.
[6] S. Naik, F. Agricola, and W. Maly, “Failure Analysis of High Density CMOS SRAMs,” IEEE Design and Test of Computers, vol. 10, no. 2, pp. 13-23, 1993.
[7] A.J. van de Goor and Z. Al-Ars, “Functional Memory Faults: A Formal Notation and a Taxonomy,” Proc. IEEE VLSI Test Symp., pp. 281-289, 2000.
[8] R. Dekker, A Realistic Fault Model and Test Algorithms for Static Random Access Memories IEEE Trans. Computers, vol. 39, no. 6, pp. 567-572, June 1990.
[9] A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk, March LA: A Test for Linked Memory Faults Proc. European Design and Test Conf., pp. 627-627, 1997.
[10] A. Jee and F.J. Ferguson, "Carafe: An Inductive Fault Analaysis Tool for CMOS VLSI Circuits," Proc. IEEE VLSI Test Symp., pp. 92-98, 1993.
[11] C.L. Henderson, J.M. Soden, and C.F. Hawkins, "The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits," Proc. Int'l Test Conf. (ITC 98), IEEE Press, Piscataway, N.J., 1998, pp. 302.
[12] Z. Al-Ars, “Analysis of the Space of Functional Fault Models and Its Application to Embedded DRAMs,” Technical Report no. 1-68340-28(1999)-07, CARDIT, Delft Univ. of Technology, Delft, The Netherlands, 1999.
[13] Z. Al-Ars and A.J. van de Goor, “Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs,” Proc. Design, Automation and Test in Europe, pp. 496-503, 2001.
[14] Z. Al-Ars and A.J. van de Goor, “Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs,” Proc. Asian Test Symp., pp. 282-289, 2000.

Index Terms:
Embedded DRAM, functional fault models, fault primitives, spot defects, defect simulation, dynamic faulty behavior.
Zaid Al-Ars, Ad J. van de Goor, "Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs," IEEE Transactions on Computers, vol. 52, no. 3, pp. 293-309, March 2003, doi:10.1109/TC.2003.1183945
Usage of this product signifies your acceptance of the Terms of Use.