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General Models and a Reduction Design Technique for FPGA Switch Box Designs
January 2003 (vol. 52 no. 1)
pp. 21-30

Abstract—An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a routing requirement over the switch box. Comparing with the known “universal switch modules,” where only 2-pin nets are considered, the hyper-universal switch box model is more general and powerful. This paper studies the generic problem and proposes a systematic designing methodology for hyper-universal (k, W){\hbox{-}}{\rm switch} boxes, where k is the number of sides and W is the number of terminals on each side. We formulate this hyper-universal (k, W){\hbox{-}}{\rm switch} box design problem as a k{\hbox{-}}{\rm partite} graph design problem and propose an efficient reduction design technique. Applying this technique, we can design hyper-universal (k, W){\hbox{-}}{\rm switch} boxes with low O(W) switches for any fixed k. For illustration, we provide optimum hyper-universal (2, W) and (3, W){\hbox{-}}{\rm switch} boxes and a hyper-universal (4, W){\hbox{-}}{\rm switch} box with switch number quite close to the lower bound 6W, which is used in a well-known commercial design without hyper-universal routability. We also conclude that the proposed reduction method can yield an efficient detailed routing algorithm for any given routing requirement as well.

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Index Terms:
FPGA, switch box, global routing, detailed routing, hyper-universal, optimum design, reduction technique.
Citation:
Hongbing Fan, Jiping Liu, Yu-Liang Wu, "General Models and a Reduction Design Technique for FPGA Switch Box Designs," IEEE Transactions on Computers, vol. 52, no. 1, pp. 21-30, Jan. 2003, doi:10.1109/TC.2003.1159751
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