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Diminished-One Modulo 2^n +1 Adder Design
December 2002 (vol. 51 no. 12)
pp. 1389-1399

Abstract—This paper presents two new design methodologies for modulo 2^n + 1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. VLSI realizations of the proposed circuits in a standard-cell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry look-ahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallel-prefix adders are considerably faster than any other already known in the open literature.

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Index Terms:
Modulo $\big. 2^{\rm n}+1\bigr.$ addition, carry look-ahead addition, parallel-prefix adders, diminished-one number representation, VLSI adders.
Citation:
Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, "Diminished-One Modulo 2^n +1 Adder Design," IEEE Transactions on Computers, vol. 51, no. 12, pp. 1389-1399, Dec. 2002, doi:10.1109/TC.2002.1146705
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