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Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, "DiminishedOne Modulo 2^n +1 Adder Design," IEEE Transactions on Computers, vol. 51, no. 12, pp. 13891399, December, 2002.  
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@article{ 10.1109/TC.2002.1146705, author = {Haridimos T. Vergos and Costas Efstathiou and Dimitris Nikolos}, title = {DiminishedOne Modulo 2^n +1 Adder Design}, journal ={IEEE Transactions on Computers}, volume = {51}, number = {12}, issn = {00189340}, year = {2002}, pages = {13891399}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2002.1146705}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  DiminishedOne Modulo 2^n +1 Adder Design IS  12 SN  00189340 SP1389 EP1399 EPD  13891399 A1  Haridimos T. Vergos, A1  Costas Efstathiou, A1  Dimitris Nikolos, PY  2002 KW  Modulo $\big. 2^{\rm n}+1\bigr.$ addition KW  carry lookahead addition KW  parallelprefix adders KW  diminishedone number representation KW  VLSI adders. VL  51 JA  IEEE Transactions on Computers ER   
Abstract—This paper presents two new design methodologies for modulo 2^n + 1 addition in the diminishedone number system. The first design methodology leads to carry lookahead, whereas the second to parallelprefix adder implementations. VLSI realizations of the proposed circuits in a standardcell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry lookahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallelprefix adders are considerably faster than any other already known in the open literature.
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