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Issue No.11 - November (2002 vol.51)
pp: 1282-1293
ABSTRACT
<p><b>Abstract</b>—We describe a built-in test pattern generation method for scan circuits. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The sets are stored on-chip and the on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time. We describe two schemes for reducing the set sizes, one where each set stores the values of one subset of primary inputs or state variables and one where a single set is used to store values of different subsets of state variables. We demonstrate the effectiveness of the proposed method as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults. In the latter case, the proposed method is applied to detect the hard-to-detect faults that remain undetected.</p>
INDEX TERMS
Built-in testing, Cartesian product, scan circuits.
CITATION
Irith Pomeranz, "A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set", IEEE Transactions on Computers, vol.51, no. 11, pp. 1282-1293, November 2002, doi:10.1109/TC.2002.1047753
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