This Article 
 Bibliographic References 
 Add to: 
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set
November 2002 (vol. 51 no. 11)
pp. 1282-1293

Abstract—We describe a built-in test pattern generation method for scan circuits. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The sets are stored on-chip and the on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time. We describe two schemes for reducing the set sizes, one where each set stores the values of one subset of primary inputs or state variables and one where a single set is used to store values of different subsets of state variables. We demonstrate the effectiveness of the proposed method as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults. In the latter case, the proposed method is applied to detect the hard-to-detect faults that remain undetected.

[1] V. Iyengar, K. Chakrabarty, and B.T. Murray, “Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets,” Proc. VLSI Test Symp., pp. 418-422, Apr. 1998.
[2] R. Dandapani, J.H. Patel, and J.A. Abraham, “Design of Test Pattern Generation for Built-In Test,” Proc. Int'l Test Conf., pp. 315-319, 1984.
[3] I. Pomeranz and S.M. Reddy, “Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences,” Proc. 36th Design Automation Conf., pp. 754-759, June 1999.
[4] S. Ma, P. France, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques: Experimental Results," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1995, pp. 663-672.
[5] J.T.-Y. Chang, C.-W. Tseng, C.-M.J. Li, M. Purtell, and E.J. McCluskey, Analysis of Pattern-Dependent and Timing-Dependent Failures in an Experimental Test Chip Proc. 1998 Int'l Test Conf., pp. 184-193, Oct. 1998.
[6] P.C. Maxwell, R.C. Aitken, K.R. Kollitz, and A.C. Brown, “IDDQ and AC Scan: The War Against Unmodelled Defects,” Proc. 1996 Int'l Test Conf., pp. 250-258, Oct. 1996.
[7] “Best Methods for At-Speed Testing?” Proc. 16th VLSI Test Symp., Panel 3, p. 460, Apr. 1998.
[8] H.-C. Tsai, K.-T. Cheng, and S. Bhawmik, “Improving the Test Quality for Scan-Based BIST Using General Test Application Scheme,” Proc. Design Automation Conf., pp. 748-753, June 1999.
[9] Y. Huang, I. Pomeranz, S.M. Reddy, and J. Rajski, “Improving the Proportion of At-Speed Tests in Scan BIST,” Proc. Int'l Conf. Computer-Aided Design, Nov. 2000.
[10] I. Pomeranz, “Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits,” Proc. 38th Design Automation Conf., pp. 145-150, June 2001.
[11] D.A. Forsyth and J. Ponce, Computer Vision: A Modern Approach. Prentice Hall, 2002.
[12] C.H. Chen and S.K. Gupta, A Methodology to Design Efficient BIST Test Pattern Generators Proc. Int'l Test Conf., pp. 814-823, 1995.
[13] K. Chakrabarty and B.T. Murray, Design of Built-In Test Generator Circuits Using Width Compression IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 1044-1051, Oct. 1998.
[14] S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” Proc. 2000 Int'l Test Conf., pp. 778-784, Oct. 2000.
[15] L. Li and Y. Min, “An Efficient BIST Design Using LFSR-ROM Architecture,” Proc. Ninth Asian Test Symp., pp. 386-390, Nov. 2000.
[16] H. Liang, S. Hellebrand, and H.J. Wunderlich, Two Dimensional Test Data Compression for Scan-Based Deterministic BIST Proc. Int'l Test Conf., pp. 894-902, Oct. 2001.
[17] K. Chakrabarty, B.T. Murray, and V. Iyengar, “Deterministic Built-In Test Pattern Generation for High-PerformanceCircuits Using Twisted-Ring Couters,” IEEE Trans. VLSI Systems, pp. 633-636, Oct. 2000.
[18] S. Kajihara, I. Pomeranz, K. Kinoshita, and S.M. Reddy, “Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits,” IEEE Trans. Computer-Aided Design, pp. 1496-1504, Dec. 1995.
[19] I. Pomeranz and S.M. Reddy, Static Test Compaction for Scan-Based Designs to Reduce Test Application Time Proc. IEEE Asian Test Symp., pp. 198-203, Dec. 1998.
[20] I. Pomeranz and S.M. Reddy, “Simulation Based Test Generation for Scan Designs,” Proc. Int'l Conf. Computer-Aided Design, pp. 544-549, Nov. 2000.

Index Terms:
Built-in testing, Cartesian product, scan circuits.
Irith Pomeranz, Sudhakar M. Reddy, "A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set," IEEE Transactions on Computers, vol. 51, no. 11, pp. 1282-1293, Nov. 2002, doi:10.1109/TC.2002.1047753
Usage of this product signifies your acceptance of the Terms of Use.