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Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors
October 2002 (vol. 51 no. 10)
pp. 1269-1280

Abstract—In this paper, we propose a framework for analyzing the flow of values and their reuse in loop nests to minimize data traffic under the constraints of limited on-chip memory capacity and dependences. Our analysis first undertakes fusion of possible loop nests intra-procedurally and then performs loop distribution. The analysis discovers the closeness factor of two statements which is a quantitative measure of data traffic saved per unit memory occupied if the statements, were under the same loop nest over the case where they are under different loop nests. We then develop a greedy algorithm which traverses the program dependence graph (PDG) to group statements together under the same loop nest legally to promote maximal reuse per unit of memory occupied. We implemented our framework in Petit, a tool for dependence analysis and loop transformations. We compared our method with one based on tiling of fused loop nest and one based on a greedy strategy to purely maximize reuse. We show that our methods work better than both of these strategies in most cases for processors such as TMS320Cxx, which have a very limited amount of on-chip memory. The improvements in data I/O range from 10 to 30 percent over tiling and from 10 to 40 percent over maximal reuse for JPEG loops.

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Index Terms:
Loop fusion, limited memory, embedded processors, data locality, program dependence graph.
Citation:
Waibhav Tembe, Santosh Pande, "Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors," IEEE Transactions on Computers, vol. 51, no. 10, pp. 1269-1280, Oct. 2002, doi:10.1109/TC.2002.1039852
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