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Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
July 2002 (vol. 51 no. 7)
pp. 750-758

Bit-parallel finite field multiplication using polynomial basis can be realized in two steps: polynomial multiplication and reduction modulo the irreducible polynomial. In this article, we present an upper complexity bound for the modular polynomial reduction. When the field is generated with an irreducible trinomial, closed form expressions for the coefficients of the product are derived in term of the coefficients of the multiplicands. Complexity of the multiplier architectures and their critical path length is evaluated and they are comparable to the previous proposals for the same class of fields. Analytical form for bit-parallel squaring operation is also presented. The complexities for bit-parallel squarer are also derived when an irreducible trinomial is used. Consequently, it is argued that to solve multiplicative inverse using polynomial basis can be at least as good as using normal basis.

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Index Terms:
Finite fields arithmetic, hardware architecture, polynomial basis.
Citation:
Huapeng Wu, "Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis," IEEE Transactions on Computers, vol. 51, no. 7, pp. 750-758, July 2002, doi:10.1109/TC.2002.1017695
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