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Efficient Tests for Realistic Faults in Dual-Port SRAMs
May 2002 (vol. 51 no. 5)
pp. 460-473

This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with the conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings will be prevented, has been emphasized. Next, the paper presents a methodology to design tests for realistic unique dual-port memory faults, resulting in a set of three linear single-addressing tests which are merged into a single march test (March s2PF), and one linear double-addressing test (March d2PF). March s2PF and March d2PF have been implemented at Intel. The results show that they detect unique faults, i.e., faults that cannot be detected with conventional single-port memory tests. This make them very attractive industrially.

[1] M. Inoue et al., “A New Test Evaluation Chip for Lower Cost Memory Tests,” IEEE Design and Test of Computers, vol. 10, no. 1, pp. 15-19, Mar. 1993.
[2] M.J. Raposa, “Dual Port Static RAM Testing,” Proc. IEEE Int'l Test Conf., pp. 362-368, 1988.
[3] B. Nadeau-Dostie, A. Silburt, and V.K. Agarwal, "Serial Interface for Embedded-Memory Testing," IEEE Design&Test of Computers, Vol. 7, No. 2, Apr. 1990, pp. 52-63.
[4] T. Matsumura, “An Efficient Test Method for Embedded Multi-Port RAM with BIST Circuitry,” Records 1995 IEEE Int'l Workshop Memory Technology, Design, and Testing, pp. 62-67, 1995.
[5] S.W. Wood et al., “A 5Gb/s 9-Port Application Specific SRAM with Built-in Self-Test,” Records 1995 IEEE Int'l Workshop Memory Technology, Design and Testing, pp. 68-73, 1995.
[6] Y. Wu and S. Gupta, “Built-In Self Testing for Multi-Port RAMs,” Proc. Sixth Asian Test Symp., pp. 398-403, 1997.
[7] V.C. Alves and M. Nicolaidis, “Detecting Complex Coupling Faults in Multi-Port RAMs,” IMAG Research Report No. RR978, Feb. 1991.
[8] M. Nicolaidis, V. Castro Alves, and H. Bederr, "Testing Complex Couplings in Multiport RAMs," IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 59-71, Mar. 1995.
[9] A.J. van de Goor and S. Hamdioui, “Fault Models and Tests for Two-Port Memories,” Proc. 16th IEEE VLSI Test Symp., pp. 401-410, April 1998.
[10] S. Hamdioui and A.J. van de Goor, “Consequences of Port Restrictions on Testing Two-Port Memories,” Proc. Int'l Test Conf. (ITC '98), pp. 63-72, Oct. 1998.
[11] S. Hamdioui and A.J. van de Goor, “Port Interference Faults in Two-Port Memories,” Proc. Int'l Test Conf. (ITC '99) pp. 1001-1010, Sept. 1999.
[12] J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, “Detection of Inter-Port Faults in Multi-Port Static RAMs,” Proc. VLSI Test Symp., pp. 297-302, 2000.
[13] S. Hamdioui, “Testing Multi-Port Memories: Theory and Practice,” technical report, Delft Univ. of Technology, Faculty of Information Technology and Systems, Section of Computer Eng., Delft, The Netherlands, Oct. 2000.
[14] S. Hamdioui and A.J. van de Goor, “An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests,” Proc. Ninth Asian Test Symp., pp. 131-138, 2000.
[15] M.S. Abadir and J.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,” ACM Computer Surveys, vol. 15, no. 3, pp. 175-198, 1983.
[16] A. Van de Goor, Testing Semiconductor Memories, John Wiley&Sons, New York, 1991.
[17] A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk, March LR: A Test for Realistic Linked Faults Proc. 14th VLSI Test Symp., pp. 272-280, 1996.
[18] R.D. Adams, “Extension of Static Random Access Memories, Modeling and Examination of Pattern for Fault Detection,” master of science thesis, Thayer School of Engineering, Dartmouth College, Hanover, New Hampshire, May 1991.
[19] R. Dekker, A Realistic Fault Model and Test Algorithms for Static Random Access Memories IEEE Trans. Computers, vol. 39, no. 6, pp. 567-572, June 1990.
[20] M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,” Proc. Int'l Test Conf., pp. 236-239, 1982.

Index Terms:
Multiport/single-port memories, fault models, weak faults, march tests, fault coverage
S. Hamdioui, A.J. van de Goor, "Efficient Tests for Realistic Faults in Dual-Port SRAMs," IEEE Transactions on Computers, vol. 51, no. 5, pp. 460-473, May 2002, doi:10.1109/TC.2002.1004586
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