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Test Bus Sizing for System-on-a-Chip
May 2002 (vol. 51 no. 5)
pp. 449-459

System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.

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Index Terms:
Core-based systems, embedded core testing, integer linear programming, linearization, test access mechanism (TAM), test bus, testing time
Citation:
V. Iyengar, K. Chakrabarty, "Test Bus Sizing for System-on-a-Chip," IEEE Transactions on Computers, vol. 51, no. 5, pp. 449-459, May 2002, doi:10.1109/TC.2002.1004585
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