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| V. Iyengar, K. Chakrabarty, "Test Bus Sizing for System-on-a-Chip," IEEE Transactions on Computers, vol. 51, no. 5, pp. 449-459, May, 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2002.1004585, author = {V. Iyengar and K. Chakrabarty}, title = {Test Bus Sizing for System-on-a-Chip}, journal ={IEEE Transactions on Computers}, volume = {51}, number = {5}, issn = {0018-9340}, year = {2002}, pages = {449-459}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2002.1004585}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Test Bus Sizing for System-on-a-Chip IS - 5 SN - 0018-9340 SP449 EP459 EPD - 449-459 A1 - V. Iyengar, A1 - K. Chakrabarty, PY - 2002 KW - Core-based systems KW - embedded core testing KW - integer linear programming KW - linearization KW - test access mechanism (TAM) KW - test bus KW - testing time VL - 51 JA - IEEE Transactions on Computers ER - | |||
System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.
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