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Test Bus Sizing for System-on-a-Chip
May 2002 (vol. 51 no. 5)
pp. 449-459

System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.

[1] J. Aerts and E.J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based ICs,” Proc. Int'l Test Conf., pp. 448-457, 1998.
[2] M. Berkelaar, lpsolve, version 3.0. Eindhoven Univ. of Technology, Design Automation Section, Eindhoven, The Netherlands, 2000.
[3] K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming,” Proc. VLSI Test Symp., pp. 127-134, 2000.
[4] K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints,” Proc. Design Automation Conf., pp. 432-437, 2000.
[5] S. Davidson, P1500 Benchmarking Task Force Chair, private correspondence, Dec. 1999.
[6] I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Testing Technique for Core-Based System-on-Chip,” Proc. Design Automation Conf., pp. 542-547, 1998.
[7] P. Harrod, “Testing Re-Usable IP: A Case Study,” Proc. Int'l Test Conf., pp. 493-498, 1999.
[8] V. Immaneni and S. Raman, "Direct Access Test Scheme—Design of Block and Core Cells for Embedded ASICs," Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1990, pp. 488-492.
[9] International Technology Roadmap for Semiconductors. Semiconductor Industry Assoc., Home.htm. 1999.
[10] E.J. Marinissen et al., "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores," Proc. IEEE Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1998, pp. 284-293.
[11] E.J. Marinissen, S. Goel, and M. Lousberg, "Wrapper Design for Embedded Core Test," Proc. Int'l Test Conf. (ITC), IEEE Press, Piscataway, N.J., 2000, pp. 911-920.
[12] N.A. Touba and B. Pouya, “Using Partial Isolation Rings to Test Core-Based Designs,” IEEE Design and Test of Computers, vol. 14, pp. 52-59, Oct./Dec. 1997.
[13] P. Varma and S. Bhatia, "A Structured Test Re-Use Methodology for Core-Based System Chips," Proc. IEEE Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1998, pp. 294-302.

Index Terms:
Core-based systems, embedded core testing, integer linear programming, linearization, test access mechanism (TAM), test bus, testing time
V. Iyengar, K. Chakrabarty, "Test Bus Sizing for System-on-a-Chip," IEEE Transactions on Computers, vol. 51, no. 5, pp. 449-459, May 2002, doi:10.1109/TC.2002.1004585
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