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Automatic Parallelization of Compiled Event Driven VHDL Simulation
April 2002 (vol. 51 no. 4)
pp. 380-394

In this paper, we present approaches and algorithms for parallelization of compiled event driven VHDL simulations on shared-memory multiprocessors (SMP). An efficient single-threaded algorithm for simulation of VHDL descriptions is first presented. This algorithm is shown to be competitive with a commercial VHDL simulator. Schemes for multithreaded execution of this algorithm are then described. These have been implemented on top of the POSIX pthreads library and experimental results have been shown on a Sun SparcServer 1000E. Speedups of up to four on eight processors have been achieved for some benchmarks.

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Index Terms:
event driven simulation, compiled simulation, VHDL, scheduling, partitioning, multithreading, automatic parallelization
Citation:
V. Kirshnaswamy, G. Hasteer, P. Banerjee, "Automatic Parallelization of Compiled Event Driven VHDL Simulation," IEEE Transactions on Computers, vol. 51, no. 4, pp. 380-394, April 2002, doi:10.1109/12.995448
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