This Article 
 Bibliographic References 
 Add to: 
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
February 2002 (vol. 51 no. 2)
pp. 229-234

This paper tackles the open problem of designing combinational self-testing checkers (STCs) for K-pair 2-rail codes which are self-testing, even by a subset of codewords, such that some input lines are 0 (or 1) for only one input codeword. The checker presented here has both theoretical and practical importance. It is useful, e.g., to build STCs for other systematic error detecting codes like Berger codes with I=2k-1 data bits and arithmetic codes with the check base A=2k-1+1, K=3, 4, 5,....It also allows the designers to build functional totally self-checking circuits with 100 percent fault coverage in which such 2-rail codes could not have been used otherwise.

[1] W.C. Carter and P.R. Schneider, “Design of Dynamically Checked Computers,” Proc. IFIP Conf., pp. 878-883, Aug. 1968.
[2] D.A. Anderson and G. Metze, “Design of Totally Self-Checking Check Circuits form-Out-of-nCodes,” IEEE Trans. Computers, vol. 22, no. 3, pp. 263-269, Mar. 1973.
[3] M.J. Ashjaee and S.M. Reddy, “On Totally Self-Checking Checkers for Separable Codes,” IEEE Trans. Computers, vol. 26, no. 8, pp. 737-744, Aug. 1977.
[4] J.F. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications. New York: North-Holland, 1978.
[5] S.J. Piestrak, “Self-Testing Checkers for All Arithmetic Codes with Any Check Base$A$,” Proc. '91 PRFTS—The 1991 Pacific Rim Int'l Symp. Fault-Tolerant Systems, pp. 162-167, Sept. 1991.
[6] M.A. Marouf and A.D. Friedman, “Design of Self-Checking Checkers for Berger Codes,” Digest Papers Eighth Int'l Fault-Tolerant Computing Symp., pp. 179-184, June 1978.
[7] S.J. Piestrak, “Design of Fast Self-Testing Checkers for Berger Codes,” IEEE Trans. Computers, vol. 36, no. 5, pp. 629-634, May 1987.
[8] S.J. Piestrak,"The Minimal Test Set for Sorting Networks and the Use of Sorting Networks in Self-Testing Checkers for Unordered Codes," Digest of Papers 20th Int'l FTC Symp., Newcastle upon Tyne, U.K. pp. 457-464, June 1990.
[9] S.J. Piestrak, Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Scientific Papers of the Inst. of Technological Cybernetics of the Technnical Univ. of Wroclaw, no. 92, Ser.: Monographs no. 24, Oficyna Wyd. Polit. Wrocl. 1995.
[10] S.J. Piestrak, “Design of Encoders and Self-Testing Checkers for Some Systematic Unidirectional Error Detecting Codes,” J. Microelectronic Systems Integration, vol. 5, no. 4, pp. 247-260, 1997.
[11] S.J. Piestrak, “Design of TSC Code-Cisjoint Inverter-Free PLAs for Separable Unordered Codes,” Proc. Int'l Conf. Computer Design (ICCD '94), pp. 128-131, Oct. 1994.
[12] J. Khakbaz and E.J. McCluskey, “Self-Testing Embedded Parity Checkers,” IEEE Trans. Computers, vol. 33, no. 8, pp. 753-756, Aug. 1984.
[13] D. Nikolos, “Self-Testing Embedded Two-Rail Checkers,” J. Electronic Testing: Theory and Applications, vol. 12, no. 1, pp. 69-79, 1998.
[14] F. Özgüner, “Design of Totally Self-Checking Embedded Two-Rail Code Checkers,” Electronics Letters, vol. 27, pp. 382-384, Feb. 1991.
[15] E. Fujiwara and K. Matsuoka, "A Self-Checking Generalized Prediction Checkers and Its Use for Built-In Testing," IEEE Trans. Computers, vol. 36, no. 1, pp. 86-93, Jan. 1987.
[16] T.R.N. Rao, G.L. Feng, M.S. Kolluru, and J.-C. Lo, “Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning,” IEEE Trans. Computers, vol. 42, no. 8, pp. 1020-1024, Aug. 1993; see also Correction in IEEE Trans. Computers, vol. 43, no. 5, p. 640, May 1994.
[17] S.J. Piestrak, “Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning',” IEEE Trans. Computers, to appear.
[18] J.E. Smith, “The Design of Totally Self-Checking Check Circuits for a Class of Unordered Codes,” J. Design Automation Fault-Tolerant Computers, vol. 2, pp. 321-342, Oct. 1977.
[19] M. Diaz et al., “Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines,” IEEE Trans. Computers, vol. 28, no. 3, pp. 276-281, Mar. 1979.
[20] S.J. Piestrak, “PLA Implementation of Totally Self-Checking Circuits Usingm-Out-of-nCodes,” Proc. Int'l Conf. Computer Design (ICCD '85) pp. 777-781, Oct. 1985.
[21] S.J. Piestrak, “Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes,” IEEE Trans. Computers, vol. 39, no. 3, pp. 360-374, Mar. 1990.
[22] S.J. Piestrak, “General Design Principles of Self-Testing Code-Disjoint PLAs,” Proc. ATS '93—Second Asian Test Symp., pp. 287-292, Nov. 1993.
[23] S.J. Piestrak, “Design Method of Self-Testing Checkers for 1-Out-of-nCodes,” Proc. FTSD 6—Sixth Int' Conf. Fault-Tolerant Systems and Diagnostics, pp. 57-63, Sept. 1983.

Index Terms:
Berger code, concurrent error detection, embedded circuit, inverter-free circuit, self-testing checker, totally self-testing circuit, two-rail code.
S.J. Piestrak, "Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes," IEEE Transactions on Computers, vol. 51, no. 2, pp. 229-234, Feb. 2002, doi:10.1109/12.980010
Usage of this product signifies your acceptance of the Terms of Use.