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High-Speed and Reduced-Area Modular Adder Structures for RNS
January 2002 (vol. 51 no. 1)
pp. 84-89

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we are introducing a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.

[1] N. Szabo and R. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw-Hill, 1967.
[2] Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, M. Soderstrand, M.AW. Jenkins, G. Jullien, and F. Taylor, eds. New York: IEEE Press, 1986.
[3] E.D. Claudio et al., Fast Combinatorial RNS Processors for DSP Applications IEEE Trans. Computers, vol. 44, pp. 624-633, 1995.
[4] G. Alia and E. Martinelli, “A VLSI Modulo m Multiplier,” IEEE Trans. Computers, vol. 40, no. 7, pp. 873-878, July 1991.
[5] K. Elleithy and M. Bayoumi, “A Systolic Architecture for Modulo Multiplication,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, pp. 725-729, Nov. 1995.
[6] A. Hiasat, “New Efficient Structure for a Modular Multiplier for RNS,” IEEE Trans. Computers, vol. 49, no. 2, pp. 170-174, Feb. 2000.
[7] D. Dimauro, S. Impedovo, and G. Pirlo, “A New Technique for Fast Number Comparison in Residue Number System,” IEEE Trans. Computers, vol. 42, no. 5, pp. 608-612, May 1993.
[8] S.J. Piestrak, "Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders," IEEE Trans. Computers, vol. 43, no. 1, pp. 68-77, Jan. 1994.
[9] A. Premkumar, “An RNS to Binary Converter in a Three Moduli Set with Common Factors,” IEEE Trans. Circuits and Systems II, vol. 42, pp. 298-301, Apr. 1995.
[10] F. Pourbigharaz and H. Yassine, “A Signed-Digit Architecture for Residue to Binary Transformation,” IEEE Trans. Computers, vol. 46, no. 10, pp. 1146-1150, Oct. 1997.
[11] A.A. Hiasat and H.S. Abdel-Aty-Zohdy, Residue-to-Binary Arithmetic Converter for the Moduli Set$({\rm 2^k,2^k-1,2^{k-1}-1})$ IEEE Trans. Circuits and Systems-II, vol. 45, no. 2, pp. 204-209, Feb. 1998.
[12] V. Paliouras and T. Stouraitis, Multifunction Architectures for RNS Processors IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no. 8, pp. 1041-1054, Aug. 1999.
[13] Y. Wang, “Residue-to-Binary Converters Based on New Chinese Remainder Theorems,” IEEE Trans. Circuits and Systems II, vol. 47, pp. 197-205, Mar. 2000.
[14] F. Taylor, A Single Modulus ALU for Signal Processing IEEE Trans. Acoustics, Speech, Signal Processing, vol. 33, pp. 1302-1315, 1985.
[15] D. Banerji, “A Novel Implementation Method for Addition and Subtraction in Residue Number Systems,” IEEE Trans. Computers, vol. 23, no. 1, pp. 106-109, Jan. 1974.
[16] D. Agrawal and T.R.N. Rao, “Modulo$(2^n+1)$Arithmetic Logic,” IEE J. Electronic Circuits Systems, vol. 2, pp. 186-188, Nov. 1978.
[17] M. Soderstrand, “A New Hardware Implementation of Modulo Adders for Residue Number Systems,” Proc. IEEE 26th Midwest Symp. Circuits and Systems, pp. 412-415, Aug. 1983.
[18] M. Bayoumi and G. Jullien, A VLSI Implementation of Residue Adders IEEE Trans. Circuits Systems, vol. 34, pp. 284-288, 1987.
[19] M. Dugdale, VLSI Implementation of Residue Adders Based on Binary Adders IEEE Trans. Circuits Systems II, vol. 39, pp. 325-329, 1992.
[20] S.J. Piestrak, “Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem,” Proc. Int'l Conf. Computer Design (ICCD '94), pp. 508-511, Oct. 1994.
[21] A.V. Curiger, H. Bonnenberg, and H. Kaeslin, "Regular VLSI Architectures for Multiplication Modulo (2n+ 1)," IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 990-994, July 1991.
[22] A. Wrzyszcz and D. Milford, "A New Modulo 2a+ 1 Multiplier," Proc. IEEE Int'l Conf. Computer Design, pp. 614-617,Cambridge, Mass., Oct.3-6, 1993.
[23] Y. Ma, A Simplified Architecture for Modulo$(2^n+1)$Multiplication IEEE Trans. Computers, vol. 47, no. 3, pp. 333-337, Mar. 1998.
[24] R. Zimmerman, Efficient VLSI Implementation of Modulo$(2^n\pm 1)$Addition and Multiplication Proc. 14th IEEE Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
[25] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[26] S. Waser and M.J. Flynn,Introduction to Arithmetic for Digital System Designers.New York: CBS College Publishing, 1982.

Index Terms:
Computer arithmetic, Residue Number System, modular adder, carry-lookahead adder, VLSI, hardware requirements, time delay.
Citation:
Ahmad A. Hiasat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Transactions on Computers, vol. 51, no. 1, pp. 84-89, Jan. 2002, doi:10.1109/12.980018
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