Publication 2002 Issue No. 1 - January Abstract - High-Speed and Reduced-Area Modular Adder Structures for RNS
High-Speed and Reduced-Area Modular Adder Structures for RNS
January 2002 (vol. 51 no. 1)
pp. 84-89
 ASCII Text x Ahmad A. Hiasat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Transactions on Computers, vol. 51, no. 1, pp. 84-89, January, 2002.
 BibTex x @article{ 10.1109/12.980018,author = {Ahmad A. Hiasat},title = {High-Speed and Reduced-Area Modular Adder Structures for RNS},journal ={IEEE Transactions on Computers},volume = {51},number = {1},issn = {0018-9340},year = {2002},pages = {84-89},doi = {http://doi.ieeecomputersociety.org/10.1109/12.980018},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - High-Speed and Reduced-Area Modular Adder Structures for RNSIS - 1SN - 0018-9340SP84EP89EPD - 84-89A1 - Ahmad A. Hiasat, PY - 2002KW - Computer arithmeticKW - Residue Number SystemKW - modular adderKW - carry-lookahead adderKW - VLSIKW - hardware requirementsKW - time delay.VL - 51JA - IEEE Transactions on ComputersER -

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we are introducing a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.

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