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High-Speed and Reduced-Area Modular Adder Structures for RNS
January 2002 (vol. 51 no. 1)
pp. 84-89

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we are introducing a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.

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Index Terms:
Computer arithmetic, Residue Number System, modular adder, carry-lookahead adder, VLSI, hardware requirements, time delay.
Ahmad A. Hiasat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Transactions on Computers, vol. 51, no. 1, pp. 84-89, Jan. 2002, doi:10.1109/12.980018
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