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Ahmad A. Hiasat, "HighSpeed and ReducedArea Modular Adder Structures for RNS," IEEE Transactions on Computers, vol. 51, no. 1, pp. 8489, January, 2002.  
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@article{ 10.1109/12.980018, author = {Ahmad A. Hiasat}, title = {HighSpeed and ReducedArea Modular Adder Structures for RNS}, journal ={IEEE Transactions on Computers}, volume = {51}, number = {1}, issn = {00189340}, year = {2002}, pages = {8489}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.980018}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  HighSpeed and ReducedArea Modular Adder Structures for RNS IS  1 SN  00189340 SP84 EP89 EPD  8489 A1  Ahmad A. Hiasat, PY  2002 KW  Computer arithmetic KW  Residue Number System KW  modular adder KW  carrylookahead adder KW  VLSI KW  hardware requirements KW  time delay. VL  51 JA  IEEE Transactions on Computers ER   
A modular adder is a very instrumental arithmetic component in implementing online residuebased computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a highspeed and reducedarea modular adder is an important issue. In this paper, we are introducing a new modular adder design. It is based on utilizing concepts developed to realize binarybased adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.
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