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Dhananjay S. Phatak, Tom Goff, Israel Koren, "ConstantTime Addition and Simultaneous Format Conversion Based on Redundant Binary Representations," IEEE Transactions on Computers, vol. 50, no. 11, pp. 12671278, November, 2001.  
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@article{ 10.1109/12.966499, author = {Dhananjay S. Phatak and Tom Goff and Israel Koren}, title = {ConstantTime Addition and Simultaneous Format Conversion Based on Redundant Binary Representations}, journal ={IEEE Transactions on Computers}, volume = {50}, number = {11}, issn = {00189340}, year = {2001}, pages = {12671278}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.966499}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  ConstantTime Addition and Simultaneous Format Conversion Based on Redundant Binary Representations IS  11 SN  00189340 SP1267 EP1278 EPD  12671278 A1  Dhananjay S. Phatak, A1  Tom Goff, A1  Israel Koren, PY  2001 KW  Redundant representations KW  constanttime addition KW  simultaneous format conversion KW  redundant adders KW  carrysave addition KW  signeddigit addition KW  4:2 compressor. VL  50 JA  IEEE Transactions on Computers ER   
Abstract—It is wellknown that constanttime addition, in which the execution delay is independent of operand lengths, is feasible only if the output is expressed in a redundant representation. There are many ways of introducing redundancy and the specifics of the redundant format employed can have a major impact on the performance of constanttime addition and digit set conversion. This paper presents a comprehensive analysis of constanttime addition and simultaneous format conversion. We consider full as well as partially redundant representations, where not all digit positions are redundant. The number of redundant digits and their positions can be arbitrary, yielding many possible redundant representations. Format conversion refers to changing the number and/or position of redundant digits in a representation. It is shown that such a format conversion is feasible during (i.e., simultaneous with) constant time addition, even if all three operands (the two inputs and single output) are represented in distinct redundant formats. We exploit “equalweight grouping” (EWG), wherein bits having the same weight are grouped together to achieve the constanttime addition and possible simultaneous format conversion. The analysis and data show that EWG leads to efficient implementations. We compare VLSI implementations of various constanttime addition cells and demonstrate that the conventional 4:2 compressor is the most efficient way to execute constant timeaddition. We show interesting connections to prior results and indicate possible directions for further extensions.
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