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Issue No.11 - November (2001 vol.50)
pp: 1234-1247
ABSTRACT
<p><b>Abstract</b>—Technological trends require that future scalable microprocessors be decentralized. Applying these trends toward memory systems shows that the size of the cache accessible in a single cycle will decrease in a future generation of chips. Thus, a <it>bank-exposed memory system</it> comprised of small, decentralized cache banks must eventually replace that of a monolithic cache. This paper considers how to effectively use such a memory system for sequential programs. This paper presents Maps, the software technology central to <it>bank-exposed architectures</it>, which are architectures with bank-exposed memory systems. Maps solves the problem of <it>bank disambiguation</it>—that of determining at compile-time which bank a memory reference is accessing. Bank disambiguation is important because it enables the compile-time optimization for data locality, where data can be placed close to the computation that requires it. Two methods for bank disambiguation are presented: <it>equivalence-class unification</it> and <it>modulo unrolling</it>. Experimental results are presented using a compiler for the MIT Raw machine, a bank-exposed architecture that relies on the compiler to 1) manage its memory and 2) orchestrate its instruction level parallelism and communication. Results on Raw using sequential codes demonstrate that using bank disambiguation improves performance by a factor of 3 to 5 over using ILP alone.</p>
INDEX TERMS
Compiler, memory, bank disambiguation, memory parallelism, Maps, Raw.
CITATION
Walter Lee, Saman Amarasinghe, Rajeev Barua, "Compiler Support for Scalable and Efficient Memory Systems", IEEE Transactions on Computers, vol.50, no. 11, pp. 1234-1247, November 2001, doi:10.1109/12.966497
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