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| Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal, "Compiler Support for Scalable and Efficient Memory Systems," IEEE Transactions on Computers, vol. 50, no. 11, pp. 1234-1247, November, 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/12.966497, author = {Rajeev Barua and Walter Lee and Saman Amarasinghe and Anant Agarwal}, title = {Compiler Support for Scalable and Efficient Memory Systems}, journal ={IEEE Transactions on Computers}, volume = {50}, number = {11}, issn = {0018-9340}, year = {2001}, pages = {1234-1247}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.966497}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Compiler Support for Scalable and Efficient Memory Systems IS - 11 SN - 0018-9340 SP1234 EP1247 EPD - 1234-1247 A1 - Rajeev Barua, A1 - Walter Lee, A1 - Saman Amarasinghe, A1 - Anant Agarwal, PY - 2001 KW - Compiler KW - memory KW - bank disambiguation KW - memory parallelism KW - Maps KW - Raw. VL - 50 JA - IEEE Transactions on Computers ER - | |||
Abstract—Technological trends require that future scalable microprocessors be decentralized. Applying these trends toward memory systems shows that the size of the cache accessible in a single cycle will decrease in a future generation of chips. Thus, a
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