Issue No.10 - October (2001 vol.50)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.956088
<p><b>Abstract</b>—A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated on a large area panel, and multiprocessor systems. As all the units are similar, it is critical that the test process be parallelized in order that multiple units may be tested for the cost of testing one unit. With this objective in mind, we propose a parallel and pipelined Boundary Scan Standard-based scheme for testing all units simultaneously. In this scheme, the test vectors and the corresponding correct-response vectors are both scanned into the scan chain of the units in an interleaved fashion, optimally utilizing the resources of every chain to test all units. The comparison of the expected versus the observed response of a unit is performed locally at each unit. Our algorithm provides an order of magnitude speed-up in test time over conventional boundary scan based testing schemes. Further, as the number of chains increases, the test time tends asymptotically toward the optimal. The complete design of the test architecture is also presented in the paper.</p>
Boundary scan, relay propagation test, multiprocessor systems.
Abhijit Chatterjee, Koppolu Sasidhar, "Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures", IEEE Transactions on Computers, vol.50, no. 10, pp. 1007-1019, October 2001, doi:10.1109/12.956088