This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A New Control Circuit for Asynchronous Micropipelines
September 2001 (vol. 50 no. 9)
pp. 992-997

Abstract—In this paper, we present a new configuration of an asynchronous micropipeline, called Locally Distributed Asynchronous (LDA) micropipeline, using a new control circuit. The control circuit generates local control signals according to the 4-phase signaling protocol. The control circuit is used to control the dynamic logic in the datapath. Comparisons based on simulations with other earlier published asynchronous micropipelines are also presented.

[1] Intel Corp., “Opportunistic Time-Borrowing Domino Logic,” US Patent 5,517,136, May 1996.
[2] I. Lin, J.A. Ludwig, and K. Eng, “Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches,” Proc. ACM/IEEE Design Automation Conf., pp. 393-398, June 1992.
[3] I. Sutherland, "Micropipelines," Comm. ACM, Vol. 32 No. 6, ACM Press, New York, June 1989.
[4] T.H.-Y. Meng, Parallel Algorithms and Architectures for DSP Applications: Design of Asynchronous Parallel Architectures, chapter 8, pp. 191-224, Kluwer Academic, 1991.
[5] N.C. Paver, “Design and Implementation of an Asynchronous Microprocessor,” PhD thesis, technical report, Univ. of Manchester, June 1994.
[6] S.B. Furber, P. Day, J.D. Garside, N.C. Paver, and J.V. Woods, "A Micropipelined ARM," Proc. IFIP TC 10/WG 10.5 Int'l Conf. Very Large Scale Integration (VLSI '93), T. Yanagawa and P.A. Ivey, eds. NorthHolland, Sept. 1993.
[7] J.D. Garside, S.B. Furber, and S.-H. Chung, “AMULET3 Revealed,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), pp. 51-59, 1997.
[8] A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic, and P.J. Hazewindus, "Design of an Asynchronous Microprocessor," Advanced Research in VLSI 1989: Proc. Decennial Caltech Conf. VLSI, C.L. Seitz, ed. MIT Press, 1989
[9] T.E. Williams, “Analyzing and Improving the Latency and Throughput Performance of Self-Timed Pipelines and Rings,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '92), pp. 665-668, 1992.
[10] T.E. Williams and M.A. Horowitz, "A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1,651-1,661, Nov. 1991.
[11] M. Singh and S.M. Nowick, “High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNCH 2000), pp. 198-209, 2000.
[12] G. Matsubara and N. Ide, “A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNCH '97), pp. 198-209, 1997.
[13] T.A. Chu, C.K.C. Leung, and T.S. Wanuga, “A Design Methodology for Concurrent VLSI Systems,” Proc. Int'l Conf. Computer Design (ICCD), pp. 407-410, 1985.
[14] K.Y. Yun, P.A. Beerel, and J. Arceo, “High Performance Asynchronous Pipeline Circuits,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNCH '96), pp. 17-28, 1996.
[15] S.B. Furber and J. Liu, “Dynamic Logic in Four-Phase Micropipelines,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNCH '96), pp. 11-16, 1996.
[16] T.E. Williams, “Self-Timed Rings and their Application to Division,” PhD thesis, Straford Univ., June 1991.

Index Terms:
Asynchronous design, micropipeline, zero-overhead, dual-rail coding.
Citation:
Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-fat Chan, "A New Control Circuit for Asynchronous Micropipelines," IEEE Transactions on Computers, vol. 50, no. 9, pp. 992-997, Sept. 2001, doi:10.1109/12.954514
Usage of this product signifies your acceptance of the Terms of Use.