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Issue No.09 - September (2001 vol.50)
pp: 921-934
ABSTRACT
<p><b>Abstract</b>—Directories have been used to maintain cache coherency in shared memory multiprocessors with private caches. The traditional full map directory tracks the exact caching status for each shared memory block and is designed to be efficient and simple. Unfortunately, the inherent directory size explosion makes it unsuitable for large-scale multiprocessors. In this paper, we propose a new directory scheme, dubbed associative full map directory (<tmath>$ADir_pNB$</tmath>) which reduces the directory storage requirement. The proposed <tmath>$ADir_pNB$</tmath> uses one directory entry to maintain the sharing information for a set of exclusively cached memory blocks in a centralized linked list style. By implementing dynamic cache pointer allocation, reclamation, and replacement hints, <tmath>$ADir_pNB$</tmath> can be implemented as “a full map directory with lower directory memory cost.” Our analysis indicates that, on a typical architectural paradigm, <tmath>$ADir_pNB$</tmath> reduces memory overhead of a traditional full map directory by up to 70-80 percent. In addition to the low memory overhead, we show that the proposed scheme can be implemented with appropriate protocol modification and hardware addition. Simulation studies indicate that <tmath>$ADir_pNB$</tmath> can achieve a competitive performance with the <tmath>$Dir_pNB$</tmath>. Compared with limited directory schemes, <tmath>$ADir_pNB$</tmath> shows more stable and robust performance results on applications across a spectrum of memory sharing and access patterns due to the elimination of directory overflows. We believe that <tmath>$ADir_pNB$</tmath> can be employed as a design alternative of full map directory for moderately large-scale and fine-grain shared memory multiprocessors.</p>
INDEX TERMS
Cache coherence, directory protocols, shared memory multiprocessors, computer architecture.
CITATION
Tao Li, Lizy Kurian John, "ADir_pNB: A Cost-Effective Way to Implement Full Map Directory-Based Cache Coherence Protocols", IEEE Transactions on Computers, vol.50, no. 9, pp. 921-934, September 2001, doi:10.1109/12.954507