|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, "Testing Schemes for FIR Filter Structures," IEEE Transactions on Computers, vol. 50, no. 7, pp. 674-688, July, 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/12.936234, author = {Nilanjan Mukherjee and Janusz Rajski and Jerzy Tyszer}, title = {Testing Schemes for FIR Filter Structures}, journal ={IEEE Transactions on Computers}, volume = {50}, number = {7}, issn = {0018-9340}, year = {2001}, pages = {674-688}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.936234}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Testing Schemes for FIR Filter Structures IS - 7 SN - 0018-9340 SP674 EP688 EPD - 674-688 A1 - Nilanjan Mukherjee, A1 - Janusz Rajski, A1 - Jerzy Tyszer, PY - 2001 KW - Complex multipliers KW - design for testability KW - FIR filters KW - pseudoexhaustive testing KW - sign-extended adders KW - cell fault model KW - state coverage KW - trees of adders. VL - 50 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper presents a new pseudoexhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed to detect any combinational faults within the basic cell of the functional units occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudo-exhaustive patterns to systematically test all FIR filter building blocks.
[1] V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-In Self-Test, Part 1: Principles IEEE Design and Test of Computers, pp. 73-82, Mar. 1993.
[2] V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-In Self-Test, Part 2: Applications IEEE Design and Test of Computers, pp. 69-77, June 1993.
[3] A. Chatterjee and J. Abraham, “Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model,” IEEE Trans. Computers, vol. 40, no. 10, pp. 1133-1148, Oct. 1991.
[4] C.-I.H. Chen and J.T. Yuen, “Automated Synthesis of Pseudo-Exhaustive Test Generator in VLSI BIST Design,” IEEE Trans. VLSI Systems, vol. 2, no. 3, pp. 273-291, Sept. 1994.
[5] A.D. Friedman, “A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays,” IEEE Trans. Computers, vol. 43, no. 12, pp. 1365-1375, Dec. 1994.
[6] F.G. Gray and R.A. Thompson, “Fault Detection in Bilateral Arrays of Combinational Cells,” IEEE Trans. Computers, vol. 27, no. 10, pp. 1206-1213, Oct. 1978.
[7] S. Gupta, J. Rajski, and J. Tyszer, “Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns,” IEEE Trans. Computer-Aided Design, pp. 939-949, Aug. 1996.
[8] R.J. Higgins, Digital Signal Processing in VLSI. Prentice Hall, 1990.
[9] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[10] D. Kagaris, F. Makedon, and S. Tragoudas, A Method for Pseudo-Exhaustive Test Pattern Generation IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 9, pp. 1170-1178, 1994.
[11] N. Mukherjee, “Built-In Self Test for Functional Blocks in Data Path Architectures,” PhD thesis, McGill Univ., Montreal, Canada, 1996.
[12] N. Mukherjee, M. Kassab, J. Rajski, and J. Tyszer, “Arithmetic Built-In Self-Test for High-Level Synthesis,” Proc. VTS, pp. 132-139, May 1995.
[13] Y. Neuvo, “Digital Filter Implementation Considerations,” Handbook for Digital Signal Processing, S.K. Mitra and J.K. Kaiser, eds., pp. 337-417, John Wiley&Sons, 1993.
[14] R. Parthasarathy and S.M. Reddy, “A Testable Design of Iterative Logic Arrays,” IEEE Trans. Computers, vol. 30, no. 11, pp. 833-841, Nov. 1981.
[15] J.G. Proakis and D.G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications. Prentice Hall, 1996.
[16] J. Rajski and J. Tysze, "Arithmetic Built-In Self-Test for Embedded Systems," Prentice Hall,Upper Saddle River, New Jersey, 1997.
[17] J.P. Shen and F.J. Ferguson, “The Design of Easily Testable VLSI Array Multipliers,” IEEE Trans. Computers, vol. 33, no. 6, pp. 554-557, June 1984.
[18] R. Srinivasan, S.K. Gupta, and M.A. Breuer, “Novel Test Patttern Generators for Pseudo-Exhaustive Testing,” Proc. Int'l Test Conf., pp. 1,041-1,050, Oct. 1993.
[19] C. Su and C. Wu, “Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns,” IEEE Trans. Computers, vol. 43, no. 4, pp. 495-501, Apr. 1994.
[20] A. Vergis, “On the Testability of One-Dimensional ILAs for multiple Sequential Faults,” IEEE Trans. Computers, vol. 41, no. 7, pp. 906-916, July 1992.
[21] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.