
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis, "OperationSaving VLSI Architectures for 3D Geometrical Transformations," IEEE Transactions on Computers, vol. 50, no. 6, pp. 609622, June, 2001.  
BibTex  x  
@article{ 10.1109/12.931896, author = {Konstantina Karagianni and Vassilis Paliouras and George Diamantakos and Thanos Stouraitis}, title = {OperationSaving VLSI Architectures for 3D Geometrical Transformations}, journal ={IEEE Transactions on Computers}, volume = {50}, number = {6}, issn = {00189340}, year = {2001}, pages = {609622}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.931896}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  OperationSaving VLSI Architectures for 3D Geometrical Transformations IS  6 SN  00189340 SP609 EP622 EPD  609622 A1  Konstantina Karagianni, A1  Vassilis Paliouras, A1  George Diamantakos, A1  Thanos Stouraitis, PY  2001 KW  Elementary geometrical transformations KW  VLSI architecture KW  graphics processor KW  vector unit. VL  50 JA  IEEE Transactions on Computers ER   
Abstract—Two VLSI architectures for the computationally efficient implementation of the elementary 3D geometrical transformations are introduced. The first one is based on a single floatingpoint multiply/add unit, while the other one comprises a four processingelement vector unit. By exploiting the structure of the elementary transformation matrices, some of the elements of which are ones and zeros, the proposed architectures avoid fullmatrix multiplication for the matrix multiplications involved in the calculation of the transformation matrix by treating them as updates of specific elements, the new values of which are obtained by scalar operations in the case of the singleprocessor architecture or by simple vector operations in the case of the processor array. Thus, the floatingpoint operation count and the number of memory accesses required by a transformation are reduced and, therefore, the performance of the circuit which computes the transformation matrix, in terms of execution time, is improved at minimal hardware cost. Furthermore, a circuit is proposed which, for each sequence of transformations, selects the most appropriate direction for computing the product of the matrices in the corresponding stack of transformation matrices in order to further reduce the number of floatingpoint operations compared to the case where the direction of the computation of the successive matrix products is predetermined. The proposed singleprocessor architecture is suitable for lowcost applications, while the parallel execution scheme implemented by the introduced parallel processor may be implemented by any fourPE processor with small overhead.
[1] J.D. Foley, A. Van Dam, S.K. Feiner, J.F. Hughes, and R.L. Phillips, Introduction to Computer Graphics. AddisonWesley, 1994.
[2] Digital Signal Processing Applications Using the ADSP2100 Family. Prentice Hall, 1992.
[3] “Indigo 2 IMPACT Breakthrough Graphics,” http://www.honcad.com/honcad_home/htmli2graphics.html , Nov. 1996.
[4] 82786 Graphics Coprocessor User's Manual, Intel, 1988.
[5] A. Makoto, O. Tatsushi, Y. Hideki, and S. Shigeru, “3D Graphics Processor Chip Set,” IEEE Micro, vol. 15, no. 6, pp. 3745, Dec. 1995.
[6] J.H. Clark, “The Geometry Engine: A VLSI Geometry System for Graphics,” Computer Graphics, vol. 16, pp. 127133, July 1982.
[7] H. Kubosawa, N. Higaki, S. Ando, H. Takahashi, Y. Asada, H. Anbutsu, T. Sato, M. Sakate, A. Suga, M. Kimura, H. Miyake, H. Okano, A. Asato, Y. Kimura, H. Nakayama, M. Kimoto, K. Hirochi, H. Saito, N. Kaido, Y. Nakagawa, and T. Shimada, “A 2.5GFLOPS, 6.5 Million Polygons per Second, FourWay VLIW Geometry Processor with SIMD Instructions and a Software Bypass Mechanism,” IEEE J. SolidState Circuits, vol. 34, pp. 16191626, Nov. 1999.
[8] N. Ide, M. Hirano, Y. Endo, S. Yoshioka, H. Murakami, A. Kunimatsu, T. Sato, T. Kamei, T. Okada, and M. Suzuoki, “2.44GFLOPS 300MHz FloatingPoint VectorProcessing Unit for HighPerformance 3D Graphics Computing,” IEEE J. SolidState Circuits, vol. 35, pp. 10251033, July 2000.
[9] Low Power Design Methodologies, J.M. Rabaey and M. Pedram, eds. Kluwer Academic, 1996.
[10] K. Fukushima and N. Wake, “Handwritten Alphanumeric Character Recognition by the Neocognitron,” IEEE Trans Neural Networks, vol. 2, pp. 355365, 1991.
[11] C.B. Harrell and F. Fouladi, “Graphics Rendering Architecture for a High Performance Desktop Workstation,” Proc. SIGGRAPH, pp. 9399, 1993.
[12] K.P. Acken, M.J. Irwin, R.M. Owens, and A.K. Garga, “Architectural Optimizations for a Floating Point MultiplyAccumulate Unit in a Graphics Pipeline,” Proc. Int'l Conf. Application Specific Systems, Architectures, and Processors, pp. 6571, 1996.
[13] B. Parhami, Computer Arithmetic—Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2000.
[14] V. Paliouras, K. Karagianni, and T. Stouraitis, “Error Bounds for FloatingPoint Polynomial Interpolators,” IEE Electronics Letters vol. 35, pp. 195197, Feb. 1999.
[15] J. Cao and B. Wei, “HighPerformance Hardware for Function Generation,” Proc. 13th Symp. Computer Arithmetic, pp. 184188, 1997.
[16] V. Paliouras, K. Karagianni, and T. Stouraitis, “A FloatingPoint Processor for Fast and Accurate Sine/Cosine Evaluation,” IEEE Trans. Circuits and SystemsII: Analog and Digital Signal Processing, vol. 47, pp. 441451, May 2000.
[17] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[18] M.J. Schulte and J.E. Stine, “Symmetric Bipartite Tables for Accurate Function Approximation” Proc. 13th Symp. Computer Arithmetic (ARITH13), pp. 175183, 1997.
[19] J.D. Foley et al., Computer Graphics: Principles and Practice, Second Edition in C, AddisonWesley, Reading, Mass., 1995.
[20] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.