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Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System
May 2001 (vol. 50 no. 5)
pp. 519-525
ASCII Text
x 
 
Keqin Li, Victor Y. Pan, "Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System," IEEE Transactions on Computers, vol. 50, no. 5, pp. 519-525, May, 2001.
 
 
BibTex
x
 
@article{ 10.1109/12.926164,
author = {Keqin Li and Victor Y. Pan},
title = {Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System},
journal ={IEEE Transactions on Computers},
volume = {50},
number = {5},
issn = {0018-9340},
year = {2001},
pages = {519-525},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.926164},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System
IS - 5
SN - 0018-9340
SP519
EP525
EPD - 519-525
A1 - Keqin Li,
A1 - Victor Y. Pan,
PY - 2001
KW - Bilinear algorithm
KW - cost-optimality
KW - distributed memory system
KW - linear array
KW - matrix multiplication
KW - optical pipelined bus
KW - PRAM
KW - reconfigurable system
KW - speedup.
VL - 50
JA - IEEE Transactions on Computers
ER -
 

Abstract—The known fast sequential algorithms for multiplying two $N\times N$ matrices (over an arbitrary ring) have time complexity $O(N^\alpha)$, where $2 < \alpha < 3$. The current best value of $\alpha$ is less than 2.3755. We show that, for all $1 \le p \le N^{\alpha}$, multiplying two $N\times N$ matrices can be performed on a p-processor linear array with a reconfigurable pipelined bus system (LARPBS) in $ O({N^{\alpha}\over p}+({N^2\over p^{2/\alpha}})\log p)$ time. This is currently the fastest parallelization of the best known sequential matrix multiplication algorithm on a distributed memory parallel system. In particular, for all $1 \le p \le N^{2.3755}$, multiplying two $N\times N$ matrices can be performed on a p-processor LARPBS in $ O({N^{2.3755}\over p}+({N^2\over p^{0.8419}})\log p) $ time and linear speedup can be achieved for $p$ as large as $O(N^{2.3755}/(\log N)^{6.3262})$. Furthermore, multiplying two $N\times N$ matrices can be performed on an LARPBS with $O(N^\alpha)$ processors in $O(\log N)$ time. This compares favorably with the performance on a PRAM.

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Index Terms:
Bilinear algorithm, cost-optimality, distributed memory system, linear array, matrix multiplication, optical pipelined bus, PRAM, reconfigurable system, speedup.
Citation:
Keqin Li, Victor Y. Pan, "Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System," IEEE Transactions on Computers, vol. 50, no. 5, pp. 519-525, May 2001, doi:10.1109/12.926164
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