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Keqin Li, Victor Y. Pan, "Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System," IEEE Transactions on Computers, vol. 50, no. 5, pp. 519525, May, 2001.  
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@article{ 10.1109/12.926164, author = {Keqin Li and Victor Y. Pan}, title = {Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System}, journal ={IEEE Transactions on Computers}, volume = {50}, number = {5}, issn = {00189340}, year = {2001}, pages = {519525}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.926164}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System IS  5 SN  00189340 SP519 EP525 EPD  519525 A1  Keqin Li, A1  Victor Y. Pan, PY  2001 KW  Bilinear algorithm KW  costoptimality KW  distributed memory system KW  linear array KW  matrix multiplication KW  optical pipelined bus KW  PRAM KW  reconfigurable system KW  speedup. VL  50 JA  IEEE Transactions on Computers ER   
Abstract—The known fast sequential algorithms for multiplying two
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