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Uniprocessor Virtual Memory without TLBs
May 2001 (vol. 50 no. 5)
pp. 482-499

Abstract—We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms.

[1] T. Anderson, H. Levy, B. Bershad, and E. Lazowska, “The Interaction of Architecture and Operating System Design,” Proc. Fourth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 108-120, Apr. 1991.
[2] A.W. Appel and K. Li, “Virtual Memory Primitives for User Programs,” Proc. Fourth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '91), pp. 96-107, Apr. 1991.
[3] K. Bala, M.F. Kaashoek, and W.E. Weihl, “Software Prefetching and Caching for Translation Lookaside Buffers,” Proc. First USENIX Symp. Operating Systems Design and Implementation (OSDI '94), pp. 243-253, Nov. 1994.
[4] A. Chang and M.F. Mergen,"801 Storage: Architecture and Programming," ACM Trans. Computer Systems, Vol. 6, No. 1, Feb. 1988, pp. 28-50.
[5] J.S. Chase, H.M. Levy, E.D. Lazowska, and M. Baker-Harvey, “Lightweight Shared Objects in a 64-Bit Operating System,” Technical Report 92-03-09, Univ. of Washington, Mar. 1992.
[6] J.B. Chen, A. Borg, and N.P. Jouppi, “A Simulation Based Study of TLB Performance,” Proc. 19th Ann. Int'l Symp. Computer Architecture (ISCA '92), May 1992.
[7] R. Cheng, “Virtual Address Cache in UNIX,” Proc. Summer 1987 USENIX Technical Conf., June 1987.
[8] D.R. Cheriton, G.A. Slavenburg, and P.D. Boyle, “Software-Controlled Caches in the VMP Multiprocessor,” Proc. 13th Ann. Int'l Symp. Computer Architecture (ISCA '86), Jan. 1986.
[9] D.W. Clark and J.S. Emer, "Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement," ACM Trans. Computer Systems, ACM, New York, Vol. 3, No. 1, Feb. 1985, pp. 31-62.
[10] H. Deitel, Inside OS/2. Reading, Mass.: Addison-Wesley, 1990.
[11] K. Diefendorff, “Transmeta Unveils Crusoe: Supersecret Startup Attacks Mobile Market with VLIW, Code Morphing,” Microprocessor Report, vol. 14, no. 1, pp. 15-16, Jan. 2000.
[12] Digital Equipment Corp., DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware Reference Manual. Maynard, Mass.: Digital Equipment Corp., 1994.
[13] D.R. Engler, S.K. Gupta, and M.F. Kaashoek, “AVM: Application-Level Virtual Memory,” Proc. Fifth Workshop Hot Topics in Operating Systems (HotOS-V), May 1995.
[14] Etch, Memory System Research at the University of Washington. Univ. of Washington,http:/etch.cs.washington.edu/, 1998.
[15] J.R. Goodman,"Coherency for Multiprocessor Virtual Address Caches," Proc. Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM, 1987.
[16] L. Gwennap, “Intel's P6 Uses Decoupled Superscalar Design,” Microprocessor Report, vol. 9, no. 2, Feb. 1995.
[17] D.S. Henry, “Adding Fast Interrupts to Superscalar Processors,” Technical Report Memo-366, MIT Computation Structures Group, Dec. 1994.
[18] J. Huck and J. Hays, “Architectural Support for Translation Table Management in Large Address Space Machines,” Proc. 20th Ann. Int'l Symp. Computer Architecture, pp. 39–50, May 1993.
[19] IBM and Motorola, PowerPC 601 RISC Microprocessor User's Manual. IBM Microelectronics and Motorola, 1993.
[20] B.L. Jacob and T.N. Mudge, “Specification of the PUMA Memory Management Design,” Technical Report CSE-TR-314-96, Univ. of Michigan, Aug. 1996.
[21] B. Jacob and T. Mudge, “Software-Managed Address Translation,” Proc. Third Int'l Symp. High Performance Computer Architecture, pp. 156–167, Feb. 1997.
[22] B.L. Jacob and T.N. Mudge, “A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations,” Proc. Eight Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 295-306, Oct. 1998.
[23] B.L. Jacob and T.N. Mudge, “Virtual Memory in Contemporary Microprocessors,” IEEE Micro, vol. 18, no. 4, pp. 60-75, July/Aug. 1998.
[24] B. Jacob and T. Mudge, “Virtual Memory: Issues of Implementation,” Computer, vol. 31, no. 6, pp. 33–43, June 1998.
[25] B.L. Jacob, “Software-Oriented Memory-Management Design,” PhD thesis, Univ. of Michigan, July 1997.
[26] T. Juan, T. Lang, and J.J. Navarro, “Reducing TLB Power Requirements,” Proc. 1997 IEEE Int'l Symp. Low Power Electronics and Design (ISLPED '97), pp. 196-201, Aug. 1997.
[27] G. Kane and J. Heinrich, MIPS RISC Architecture, Prentice-Hall, Englewood Cliffs, N.J., 1992.
[28] J. Liedtke and K. Elphinstone, “Guarded Page Tables on Mips R4600 or an Exercise in Architecture-Dependent Microoptimization,” Operating Systems Rev., vol. 30, no. 1, pp. 4–15, Jan. 1996.
[29] The PowerPC Architecture: A Specification for a New Family of RISC Processors, C. May, E. Silha, R. Simpson, and H. Warren, eds. San Francisco: Morgan Kaufmann, 1994.
[30] D. Nagle, R. Uhlig, T. Stanley, S. Sechrest, T. Mudge, and R. Brown, “Design Tradeoffs for Software-Managed TLBs,” Proc. 20th Ann. Int'l Symp. Computer Architecture (ISCA '93), May 1993.
[31] R. Rashid et al., "Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures," IEEE Trans. Computers, Aug. 1988, pp. 896-908.
[32] S.A. Ritchie, “TLB for Free: In-Cache Address Translation for a Multiprocessor Workstation,” Technical Report UCB/CSD 85/233, Univ. of California, May 1985.
[33] M. Rosenblum, E. Bugnion, S.A. Herrod, E. Witchel, and A. Gupta, “The Impact of Architectural Trends on Operating System Performance,” Proc. 15th ACM Symp. Operating System Principles, Dec. 1995.
[34] I. Schoinas, B. Falsafi, A.R. Lebeck, S.K. Reinhardt, J.R. Larus, and D.A. Wood, “Fine-Grain Access Control for Distributed Shared Memory,” Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '94), pp. 297-306, Oct. 1994.
[35] M.L. Scott, T.J. LeBlanc, and B.D. Marsh, “Design Rationale for Psyche, a General-Purpose Multiprocessor Operating System,” Proc. 1988 Int'l Conf. Parallel Processing, Aug. 1988.
[36] M. Talluri and M.D. Hill, “Surpassing the TLB Performance of Superpages with Less Operating System Support,” Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '94), pp. 171-182, Oct. 1994.
[37] M. Talluri, M.D. Hill, and Y.A. Khalidi, “A New Page Table for 64-Bit Address Spaces,” Proc. 15th ACM Symp. Operating Systems Principles, pp. 215–231, Dec. 1995.
[38] M. Talluri, S. Kong, M.D. Hill, and D.A. Patterson, “Tradeoffs in Supporting Two Page Sizes,” Proc. 19th Ann. Int'l Symp. Computer Architecture (ISCA '92), pp. 415-424, May 1992.
[39] C.A. Thekkath and H.M. Levy, "Hardware and Software Support for Efficient Exception Handling," Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems,San Jose, Calif., Oct. 1994.
[40] S.-Y. Tzou and D.P. Anderson, “The Performance of Message-Passing Using Restricted Virtual Memory Remapping,” Software—Practice and Experience, vol. 21, no. 3, pp. 251-267, Mar. 1991.
[41] R. Wahbe, S. Lucco, T. Anderson, and S. Graham, Efficient Software-Based Fault Isolation Proc. 14th ACM Symp. Operating System Principles, pp. 203-216, Dec. 1993.
[42] W.-H. Wang, J.-L. Baer, and H.M. Levy, “Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy,” Proc. 16th Ann. Int'l Symp. Computer Architecture (ISCA '89), pp. 140-148, June 1989.
[43] S. Weiss and J.E. Smith, POWER and PowerPC. San Francisco: Morgan Kaufmann, 1994.
[44] B. Wheeler, and B.N. Bershad,"Consistency Management for Virtually Indexed Caches," Proc. Fifth Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 1992, pp. 137-148.
[45] D.A. Wood, “The Design and Evaluation of In-Cache Address Translation,” PhD thesis, Univ. California at Berkeley, Mar. 1990.
[46] D.A. Wood, S.J. Eggers, G. Gibson, M.D. Hill, J.M. Pendleton, S.A. Ritchie, G.S. Taylor, R.H. Katz, and D.A. Patterson, “An In-Cache Address Translation Mechanism,” Proc. 13th Ann. Int'l Symp. Computer Architecture (ISCA '86), Jan. 1986.

Index Terms:
Virtual memory, virtual address translation, virtual caches, memory management, software-managed address translation, translation lookaside buffers.
Citation:
Bruce Jacob, Trevor Mudge, "Uniprocessor Virtual Memory without TLBs," IEEE Transactions on Computers, vol. 50, no. 5, pp. 482-499, May 2001, doi:10.1109/12.926161
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