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Semiconcurrent Error Detection in Data Paths
May 2001 (vol. 50 no. 5)
pp. 449-465

Abstract—A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. Attention is mainly focused on data path design. After identifying the reference architecture against which cost and performance are evaluated, a simultaneous scheduling-and-allocation strategy is presented for linear-code data flow graphs, allowing resource sharing between nominal and checking data paths. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm since it is essentially concerned with the introduction of the fault tolerance issue at high-abstraction level in any design environment. Conventional duplication with comparison, even if considered in a high-level synthesis strategy, leads to high circuit complexity increase. The proposed approach provides that the required checking periodicity is satisfied while minimizing additional functional units by means of maximum reuse of the resources available for the nominal computation as long as error detection ability is preserved. The strategy is then extended to deal with branches and loops in the data path. Risk of error aliasing due to resource sharing is analyzed.

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Index Terms:
Semiconcurrent error detection, self-checking circuits, checking periodicity, fault tolerance, high-level synthesis, data flow graph, resource minimization.
Citation:
Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami, "Semiconcurrent Error Detection in Data Paths," IEEE Transactions on Computers, vol. 50, no. 5, pp. 449-465, May 2001, doi:10.1109/12.926159
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