Publication 2001 Issue No. 5 - May Abstract - Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials
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Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials
May 2001 (vol. 50 no. 5)
pp. 385-393
 ASCII Text x Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee, "Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials," IEEE Transactions on Computers, vol. 50, no. 5, pp. 385-393, May, 2001.
 BibTex x @article{ 10.1109/12.926154,author = {Chiou-Yng Lee and Erl-Huei Lu and Jau-Yien Lee},title = {Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials},journal ={IEEE Transactions on Computers},volume = {50},number = {5},issn = {0018-9340},year = {2001},pages = {385-393},doi = {http://doi.ieeecomputersociety.org/10.1109/12.926154},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced PolynomialsIS - 5SN - 0018-9340SP385EP393EPD - 385-393A1 - Chiou-Yng Lee, A1 - Erl-Huei Lu, A1 - Jau-Yien Lee, PY - 2001KW - Bit-parallel systolic multiplierKW - finite fieldKW - AOPKW - ESP.VL - 50JA - IEEE Transactions on ComputersER -

Abstract—Two operations, the cyclic shifting and the inner product, are defined by the properties of irreducible all one polynomials. An effective algorithm is proposed for computing multiplications over a class of fields $GF(2^m)$ using the two operations. Then, two low-complexity bit-parallel systolic multipliers are presented based on the algorithm. The first multiplier is composed of $(m+1)^2$ identical cells, each consisting of one 2-input AND gate, one 2-input XOR gate, and three 1-bit latches. The other multiplier comprises of $(m+1)^2$ identical cells and mXOR gates. Each cell consists of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. Each multiplier exhibits very low latency and propagation delay and is thus very fast. Moreover, the architectures of the two multipliers can be applied in computing multiplications over the class of fields $GF(2^m)$ in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m.

Index Terms:
Bit-parallel systolic multiplier, finite field, AOP, ESP.
Citation:
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee, "Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials," IEEE Transactions on Computers, vol. 50, no. 5, pp. 385-393, May 2001, doi:10.1109/12.926154