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Inherently Lower-Power High-Performance Superscalar Architectures
March 2001 (vol. 50 no. 3)
pp. 268-285

Abstract—In recent years, reducing power has become an important design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phases of microprocessor development, in particular, the stage of defining a chip microarchitecture. We investigate power-optimization techniques of superscalar microprocessors at the microarchitecture level that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed or will be heavily consumed in next-generation superscalar processors. Then, a new, energy-efficient version of a multicluster microarchitecture is developed that reduces energy in the identified critical design points with minimal performance impact. A methodology is developed for energy-performance optimization at the microarchitecture level that generates, for a microarchitecture, a set of energy-efficient configurations, forming a convex hull in the power-performance space. Detailed simulation of the baseline and proposed multicluster architectures has been performed using the developed optimization methodology. A comparison of the two microarchitectures, both optimized for energy efficiency, shows that the multicluster architecture is potentially up to twice as energy efficient for wide issue processors, with an advantage that grows with the issue width. Conversely, at the same power dissipation level, the multicluster architecture supports configurations with measurably higher performance than equivalent conventional designs.

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Index Terms:
Low power microarchitecture, multicluster architecture, energy-efficient configurations, energy models.
Citation:
Victor V. Zyuban, Peter M. Kogge, "Inherently Lower-Power High-Performance Superscalar Architectures," IEEE Transactions on Computers, vol. 50, no. 3, pp. 268-285, March 2001, doi:10.1109/12.910816
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