This Article 
 Bibliographic References 
 Add to: 
An Optical Bus-Based Distributed Dynamic Barrier Mechanism
December 2000 (vol. 49 no. 12)
pp. 1354-1365

Abstract—Barrier synchronization is a useful parallel programming construct for ensuring that all processors are at a particular location in the code before any processor is allowed to continue. Barrier synchronization is integral to programming models such as the Bulk Synchronous Parallel model. Specialized hardware is often used to improve the performance of a barrier synchronization operation. With continued improvement in processor performance, more efficient synchronization mechanisms are required to counter the rising relative cost of synchronization operations. A high-speed, distributed barrier synchronization mechanism has been developed for broadcast-based optical interconnection networks. This mechanism avoids multiple conversions between optical and electrical signals by having each processor locally decide whether the barrier in which it is participating has been satisfied. It also allows arbitrary sized partitions to be built dynamically during the execution of a program. Simulations of the current hardware design estimate that the barrier synchronization requires less than 300ns for a 128-processor system.

[1] L.G. Valiant, “A Bridging Model for Parallel Computation,” Comm. ACM, vol. 33, no. 8, pp. 103-111, Aug. 1990.
[2] D. Hensgen,R. Finkel,, and U. Manber,“Two algorithms for barrier synchronization,” Int’l J. Parallel Programming, vol. 17, no. 1, pp. 1-17, Feb. 1988.
[3] Thinking Machines Corp., “Connection Machine CM-5 Technical Summary,” Nov. 1992.
[4] Cray Research, Inc., CRAY T3D System Architecture Overview, 1993.
[5] V. Ramakrishnan, I.D. Scherson, and R. Subramanian, “Efficient Techniques for Fast Nested Barrier Synchronization,” Proc. Seventh Ann. ACM Symp. Parallel Algorithms and Architectures, July 1995.
[6] J. Kulick, W.E. Cohen, C. Katsinis, E. Wells, A. Thomsen, R.K. Gaede, R.G. Lindquist, G.P. Nordin, M. Abushagur, and D. Shen, “The Simultaneous Optical Multiprocessor Exchange Bus,” Proc. Second Int'l Conf. Massively Parallel Processing Using Optical Interconnections, pp. 336-344, Oct. 1995.
[7] M.H. Davis Jr. and U. Ramachandran, “A Distributed Hardware Barrier in an Optical Bus-Based Distributed Shared Memory Multiprocessor,” Proc. 1992 Int'l Conf. Parallel Processing, vol. 1, pp. 228-231, Aug. 1992.
[8] R. Keryell and N. Paris, “Activity Counter: New Optimization for the Dynamic Scheduling of SIMD Control Flow,” Proc. 1993 Int'l Conf. Parallel Processing, vol. 2, pp. 184-187, Aug. 1993.
[9] W.E. Cohen, H.G. Dietz, and J.B. Sponaugle, “Dynamic Barrier Architecture for Multi-Mode Fine-Grain Parallelism Using Conventional Processors,” Proc. 1994 Int'l Conf. Parallel Processing, vol. 1, pp. 93-96, Aug. 1994.
[10] R. Gupta and M. Epstein, “High Speed Synchronization of Processors Using Fuzzy Barriers,” Int'l J. Parallel Programming, vol. 19, no. 1, pp. 53-73, 1990.
[11] D.W. Hyde, “Receiver Model for a Fully Connected Multiprocessor System,” MS thesis, Univ. of Alabama-Huntsville, 1996.
[12] Synopsys, Inc., Design Compiler Reference Manual, 2000.
[13] Mentor Graphics, Autologic VHDL Synthesis Guide, software version 8.4_1, 1994.

Index Terms:
Parallel processing, barrier synchronization, optical interconnects.
William E. Cohen, David W. Hyde, Rhonda K. Gaede, "An Optical Bus-Based Distributed Dynamic Barrier Mechanism," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1354-1365, Dec. 2000, doi:10.1109/12.895862
Usage of this product signifies your acceptance of the Terms of Use.