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An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device
December 2000 (vol. 49 no. 12)
pp. 1310-1324
ASCII Text
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Stephan Olariu, M. Cristina Pinotti, Si Qing Zheng, "An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1310-1324, December, 2000.
 
 
BibTex
x
 
@article{ 10.1109/12.895849,
author = {Stephan Olariu and M. Cristina Pinotti and Si Qing Zheng},
title = {An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device},
journal ={IEEE Transactions on Computers},
volume = {49},
number = {12},
issn = {0018-9340},
year = {2000},
pages = {1310-1324},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.895849},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device
IS - 12
SN - 0018-9340
SP1310
EP1324
EPD - 1310-1324
A1 - Stephan Olariu,
A1 - M. Cristina Pinotti,
A1 - Si Qing Zheng,
PY - 2000
KW - Special-purpose architectures
KW - hardware-algorithms
KW - sorting networks
KW - columnsort
KW - VLSI.
VL - 49
JA - IEEE Transactions on Computers
ER -
 

Abstract—We present a hardware-algorithm for sorting $N$ elements using either a p-sorter or a sorting network of fixed I/O size $p$ while strictly enforcing conflict-free memory accesses. To the best of our knowledge, this is the first realistic design that achieves optimal time performance, running in $\Theta ( {\frac{N \log N}{p \log p}})$ time for all ranges of $N$. Our result completely resolves the problem of designing an implementable, time-optimal algorithm for sorting $N$ elements using a p-sorter. More importantly, however, our result shows that, in order to achieve optimal time performance, all that is needed is a sorting network of depth $O(\log^2 p)$ such as, for example, Batcher's classic bitonic sorting network.

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[7] R. Lin, S. Olariu, J. Schwing, and J. Zhang, “Sorting in O(1) Time on a Reconfigurable Mesh of Size$n \times n$,” Parallel Computing: From Theory to Sound Practice, Proc. European Workshop Parallel Computing (EQPC '92), plenary address, pp. 16-27, 1992.
[8] M. Nigam and S. Sahni, "Sorting n Numbers on n x n Reconfigurable Meshes With Buses," Proc. Int'l Parallel Processing Symp., pp. 174-181, 1993.
[9] S. Olariu, M.C. Pinotti, and S.Q. Zheng, “How to Sort N Items Using a Sorting Network of Fixed I/O Size,” IEEE Trans. Parallel and Distributed Systems, vol. 10, no. 5, pp. 487-499, May 1999.
[10] Y. Zhang and S.Q. Zheng, “An Efficient Parallel Sorting Architecture,” VLSI Design, vol. 11, no. 2, pp. 137-147, 2000.

Index Terms:
Special-purpose architectures, hardware-algorithms, sorting networks, columnsort, VLSI.
Citation:
Stephan Olariu, M. Cristina Pinotti, Si Qing Zheng, "An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1310-1324, Dec. 2000, doi:10.1109/12.895849
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