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An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device
December 2000 (vol. 49 no. 12)
pp. 1310-1324

Abstract—We present a hardware-algorithm for sorting $N$ elements using either a p-sorter or a sorting network of fixed I/O size $p$ while strictly enforcing conflict-free memory accesses. To the best of our knowledge, this is the first realistic design that achieves optimal time performance, running in $\Theta ( {\frac{N \log N}{p \log p}})$ time for all ranges of $N$. Our result completely resolves the problem of designing an implementable, time-optimal algorithm for sorting $N$ elements using a p-sorter. More importantly, however, our result shows that, in order to achieve optimal time performance, all that is needed is a sorting network of depth $O(\log^2 p)$ such as, for example, Batcher's classic bitonic sorting network.

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Index Terms:
Special-purpose architectures, hardware-algorithms, sorting networks, columnsort, VLSI.
Citation:
Stephan Olariu, M. Cristina Pinotti, Si Qing Zheng, "An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1310-1324, Dec. 2000, doi:10.1109/12.895849
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