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| Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander, "A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1297-1309, December, 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/12.895848, author = {Hyesook Lim and Vincenzo Piuri and Earl E. Swartzlander}, title = {A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {12}, issn = {0018-9340}, year = {2000}, pages = {1297-1309}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.895848}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms IS - 12 SN - 0018-9340 SP1297 EP1309 EPD - 1297-1309 A1 - Hyesook Lim, A1 - Vincenzo Piuri, A1 - Earl E. Swartzlander, PY - 2000 KW - Application specific processor architecture KW - Discrete Cosine Transform KW - Inverse Discrete Cosine Transform KW - image compression KW - serial-parallel processor KW - systolic array. VL - 49 JA - IEEE Transactions on Computers ER - | |||
Abstract—The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.
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