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A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms
December 2000 (vol. 49 no. 12)
pp. 1297-1309

Abstract—The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.

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Index Terms:
Application specific processor architecture, Discrete Cosine Transform, Inverse Discrete Cosine Transform, image compression, serial-parallel processor, systolic array.
Citation:
Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander, "A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms," IEEE Transactions on Computers, vol. 49, no. 12, pp. 1297-1309, Dec. 2000, doi:10.1109/12.895848
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