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A Low-Power CAM Design for LZ Data Compression
October 2000 (vol. 49 no. 10)
pp. 1139-1145

Abstract—Low-power and high-performance data compressors play an increasingly important role in the portable mobile computing and wireless communication markets. Among lossless data compression algorithms for hardware implementation, LZ77 is one of the most widely used. For real-time communication, some hardware LZ compressors/decompressors have been proposed in the past. Content addressable memory (CAM) is widely considered as the most efficient architecture for pattern matching required by the LZ77 compression process. In this paper, we propose a low-power CAM-based LZ77 data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Moreover, using the proposed conditional comparison mechanism and the novel CAM cell with the NAND-type matching logic, on average we have close to two orders of improvement on power consumption, i.e., a reduction of more than 98 percent for 8-bit words. Speed is sacrificed if we use the NAND-type matching logic, but the NAND-type logic and the NOR-type logic can be combined to provide the best solution that balances power and delay. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted.

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Index Terms:
Associative memory, content addressable memory, data compression, low power design, LZ77 algorithm, semiconductor memory.
Citation:
Kun-Jin Lin, Cheng-Wen Wu, "A Low-Power CAM Design for LZ Data Compression," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1139-1145, Oct. 2000, doi:10.1109/12.888055
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