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New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
October 2000 (vol. 49 no. 10)
pp. 1120-1125

Abstract—In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C + AB2 in finite fields GF(2m). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2m). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

[1] W.W. Peterson and E.J. Weldon Jr., Error-Correcting Codes. Cambridge, Mass.: MIT Press, 1972.
[2] D.E.R. Denning, Cryptography and Data Security. Addison-Wesley, 1983.
[3] C.-S. Yeh, I.S. Reed, and T.K. Truong, “Systolic Multipliers for Finite FieldsGF(2m),” IEEE Trans. Computers, vol. 33, no. 4, pp. 357-360, Apr. 1984.
[4] P.A. Scott,S.E. Tavares, and L.E. Peppard,"A Fast VLSI Multiplier forGF(2m)," IEEE J. Selected Areas of Comm., vol. 4, pp. 62-66, Jan. 1986.
[5] I.S. Hsu,T.K. Truong,L.J. Deutsch, and I.S. Reed,"A Comparison of VLSI Architectures of Finite Field Multipliers Using Dual, Normal or Standard Bases," IEEE Trans. Computers, vol. 37, no. 6, pp. 735-737, June 1988.
[6] S. Bandyopadhyay and A. Sengupta, “Algorithms for Multiplication in Galois Field for Implementation Using Systolic Arrays,” IEE Proc., part E, vol. 135, pp. 336-339, Nov. 1988.
[7] C.-L. Wang and J.-L. Lin, “Systolic Array Implementation of Multipliers for Finite FieldsGF(2m),” IEEE Trans. Circuits and Systems, vol. 38, pp. 796-800, July 1991.
[8] S.W. Wei, “A Systolic Power-Sum Circuit for$GF(2^m)$,” IEEE Trans. Computers, vol. 43, no. 2, pp. 226-229, Feb. 1994.
[9] C.C. Wang,T.K. Truong,H.M. Shao,L.J. Deutsch,J.K. Omura, and I.S. Reed,"VLSI Architectures for Computing Multiplications and Inverses inGF(2m)," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-716, Aug. 1985.
[10] G-L. Feng,"A VLSI Architecture for Fast Iinversion inGF(2m)," IEEE Trans. Computers, vol. 38, no. 10, pp. 1,383-1,386, Oct. 1989.
[11] M. Kovac,N. Ranganathan, and M. Varanasi,"SIGMA: A VLSI Systolic Array Implementation of a Galois FieldGF(2m) Based Multiplication and Division Algorithm," IEEE Trans. VLSI Systems, vol. 1, pp. 22-30, Mar. 1993.
[12] C.L. Wang and J.L. Lin, A Systolic Architecture for Computing Inverses and Divisions in Finite Fields${\rm GF}(2^m)$ IEEE Trans. Computers, vol. 42, no. 9, pp. 1141-1146, Sept. 1993.
[13] M.A. Hasan and V.K. Bhargava,"Bit-Serial Systolic Divider and Multiplier for Finite FieldsGF(2m)," IEEE Trans. Computers, vol. 41, no. 8, pp. 972-980, Aug. 1992.
[14] S.-W. Wei, VLSI Architectures for Computing Exponentiations, Multiplicative Inverses, and Divisions in${\rm GF}(2^m)$ Proc. Int'l Symp. Circuits and Systems (ISCAS '94), pp. 203-206, 1994.
[15] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.
[16] H.T. Kung and M. Lam, “Fault Tolerant and Two Level Pipelining in VLSI Systolic Arrays,” Proc. MIT Conf. Advanced Research in VLSI, pp. 74-83, Jan. 1984.
[17] J.V. McCanny, R.A. Evans, and J.G. McWhirter, “Use of Unidirectional Data Flow in Bit-Level Systolic Array Chips,” Electronics Letters, vol. 22, pp. 540-541, May 1986.
[18] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.

Index Terms:
Finite field arithmetic, finite field division, finite field inversion, parallel-in parallel-out architecture, systolic array, VLSI.
Chin-Liang Wang, Jyh-Huei Guo, "New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1120-1125, Oct. 2000, doi:10.1109/12.888047
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