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New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
October 2000 (vol. 49 no. 10)
pp. 1120-1125

Abstract—In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C + AB2 in finite fields GF(2m). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2m). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

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Index Terms:
Finite field arithmetic, finite field division, finite field inversion, parallel-in parallel-out architecture, systolic array, VLSI.
Citation:
Chin-Liang Wang, Jyh-Huei Guo, "New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1120-1125, Oct. 2000, doi:10.1109/12.888047
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