This Article 
 Bibliographic References 
 Add to: 
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
October 2000 (vol. 49 no. 10)
pp. 1083-1099

Abstract—Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

[1] W.H. Kautz, “Testing for Faults in Cellular Logic Arrays,” Proc. Eighth Ann. Symp. Switching and Automata Theory, pp. 161-174, 1967.
[2] A.D. Friedman, “Easily Testable Iterative Systems,” IEEE Trans. Computers, vol. 22, no. 12, pp. 1,061-1,064, Dec. 1973.
[3] R. Parthasarathy and S.M. Reddy, “A Testable Design of Iterative Logic Arrays,” IEEE Trans. Computers, vol. 30, no. 11, pp. 833-841, Nov. 1981.
[4] T. Sridhar and J.P. Hayes, “Design of Easily Testable Bit-Sliced Systems,” IEEE Trans. Computers, vol. 30, no. 11, pp. 842-854, Nov. 1981.
[5] D.E. Culler and Arvind, "Resource Requirements of Dataflow Programs," Proc. Intl'l Symp. Computer Architecture, pp. 141-150, 1988.
[6] A. Chatterjee and J. Abraham, “Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model,” IEEE Trans. Computers, vol. 40, no. 10, pp. 1133-1148, Oct. 1991.
[7] A.D. Friedman, “A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays,” IEEE Trans. Computers, vol. 43, no. 12, pp. 1365-1375, Dec. 1994.
[8] T. Inoue et al., "Universal Test Complexity of Field-Programmable Gate Arrays," Proc. Fourth Asian Test Symp., IEEE Computer Society Press, Los Alamitos, Calif., 1995, pp. 259-265.
[9] C. Stroud, E. Lee, S. Konala, and M. Abramovici, “Using ILA Testing for BIST in FPGAs,” Proc. Int'l Test Conf., 1996.
[10] M. Renovell, J. Figueras, and Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to the Interconnect Structure," Proc. 15th IEEE VLSI Test Symp., IEEE CS Press, 1997, pp. 230-237.
[11] H. Konuk and F.J. Ferguson, “Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits,” Proc. IEEE Int'l Test Conf., pp. 597-606, 1997.
[12] M.H. Woods, “MOS VLSI Reliability and Yield Trends,” Proc. IEEE, vol. 74, no. 12, pp. 1,715-1,729, Dec. 1986.
[13] K. Thompson, "Intel and the Myths of Test," IEEE Design&Test of Computers, Vol. 13, No. 1, Spring 1996, pp. 79-81.
[14] R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and NMOS Integrated Circuits,” Bell System Technical J., vol. 57, no. 2, pp. 1,449-1,474, May-June 1978.
[15] J. Galiay, Y. Crouzet, and M. Vergiault, “Physical versus Logical Fault Models in MOS LSI Circuits, Impact on Their Testability,” IEEE Trans. Computers, vol. 29, no. 6, pp. 527-531, June 1980.
[16] A.K. Pramanick and S.M. Reddy, “On Detection of Delay Faults,” Proc. IEEE Int'l Test Conf., pp. 845-856, 1988.
[17] K. Heragu, J.H. Patel, and V.D. Agrawal, “Segment Delay Faults: A New Fault Model,” Proc. 14th IEEE VLSI Test Symp., pp. 32-39, 1996.
[18] G.L. Smith, “Model for Delay Faults Based upon Paths,” Proc. IEEE Int'l Test Conf., pp. 342-349, 1985.
[19] W.T. Cheng and J. Patel, “A Shortest Length Test Sequence for Sequential Fault Detection in Ripple-Carry Adders,” Proc. IEEE Int'l Conf. Computer-Aided Design, pp. 71-73, 1985.
[20] A. Vergis, “On the Testability of One-Dimensional ILAs for multiple Sequential Faults,” IEEE Trans. Computers, vol. 41, no. 7, pp. 906-916, July 1992.
[21] C. Su and C. Wu, “Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns,” IEEE Trans. Computers, vol. 43, no. 4, pp. 495-501, Apr. 1994.
[22] S.-K. Lu, C.-W. Wu, and R.-Z. Hwang, “Cell Delay Fault Testing for Iterative Logic Arrays,” J. Electronic Testing: Theory and Applications, vol. 9, no. 3, pp. 311-316, Dec. 1996.
[23] D. Gizopoulos, D. Nikolos, and A. Paschalis, “Testing CMOS Combinational Iterative Logic Arrays for Realistic Faults,” Integration: The VLSI J., vol. 21, pp. 209-228, 1996.
[24] S.M. Reddy and M.K. Reddy, “Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits,” IEEE Trans. Computers, vol. 35, no. 8, pp. 742-754, Aug. 1986.
[25] N.K. Jha and S. Kundu, Testing and Reliable Design of CMOS Circuits. Kluwer Academic, 1990.
[26] G. Craig and C. Kime, “Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults,” Proc. IEEE Int'l Test Conf., pp. 126-137, 1985.
[27] M.A. Gharaybeh, M.L. Busnell, and V.D. Agrawal, “Classification and Test Generation for Path Delay Faults Using Single Stuck-Fault Tests,” Proc. IEEE Int'l Test Conf., pp. 139-148, 1995.
[28] S. Yang, “Logic Synthesis and Optimization Benchmarks User Guide, Version 3.0,” Microelectronics Center of North Carolina (MCNC), Research Triangle Park, Jan. 1991.
[29] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design. AT&T Bell Laboratories and W.H. Freeman, 1990.
[30] S.H. Unger, Asynchronous Sequential Switching Circuits.New York: Wiley-Interscience, 1969.
[31] G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

Index Terms:
Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays.
Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian, "Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1083-1099, Oct. 2000, doi:10.1109/12.888044
Usage of this product signifies your acceptance of the Terms of Use.