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Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
October 2000 (vol. 49 no. 10)
pp. 1083-1099

Abstract—Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

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Index Terms:
Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays.
Citation:
Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian, "Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1083-1099, Oct. 2000, doi:10.1109/12.888044
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