This Article 
 Bibliographic References 
 Add to: 
Testing SRAM-Based Content Addressable Memories
October 2000 (vol. 49 no. 10)
pp. 1054-1063

Abstract—This paper presents an extensive model and algorithms for detecting faults in SRAM-based dual-port and uni-port CAMs (Content Addressable Memories). This model is based on analyzing the functionalities of a cell of an SRAM-based CAM and dividing it into two parts (storage and comparison parts). It is shown that faults can affect one or both parts. While storage faults can be detected using a traditional test algorithm (such as the March C), faults affecting the comparison part of the cell require a substantially different approach. A complete characterization of these faults is presented; by analyzing the structure of the cell in the dual and uni-port configurations, physical faults (such as stuck-at, stuck-open, stuck-on, bridge) in lines and transistors can be mapped to three functional fault sets by the execution of the comparison operation. Two new detection algorithms (directly compatible with the word-oriented March C algorithm, as widely used in existing commercial tools) are proposed; 100 percent coverage is achieved. The first algorithm (Concurrent Detection Algorithm or CDA) employs concurrent operations for testing a dual-port CAM; the second algorithm (Non Concurrent Detection Algorithm or NCDA) uses nonconcurrent operations and can be used for testing dual-port as well as uni-port CAMs. CDA requires eight passes and ($10N+2L$) tests, where $N$ is the number of words of the CAM and $L$ is the width of a word. NCDA requires eight passes, too, but ($12N+2L$) tests. The number of tests required by CDA (and NCDA, too) is significantly less than required by existing algorithms.

[1] A. Balakrishnan and J. Qian, “TLB/CAM Test Pattern Specification,” CAD, LSI Logic, June 1998.
[2] T. Kohonen, Content-Addressable Memories, Springer, Berlin, 1987.
[3] P.R. Sidorowicz and J.A. Brzozowski, “An Approach to Modeling and Testing Memories and Its Application to CAMs,” Proc. IEEE VTS, pp. 411-416, Apr. 1998.
[4] S. Kornachuk, L. McNaughton, R. Gibbins, and B. Nadeau-Dostie, “A High Speed Embedded Cache Design with Non-Intrusive VIST,” Proc. IEEE Int'l Workshop Memory, Technology, Design, and Testing, pp. 40-45, Aug. 1994.
[5] P. Mazumder, J.H. Patel, and W.K. Fuchs, “Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories,” Proc. ACM/IEEE Design Automation Conf., pp. 688-694, 1987.
[6] G. Giles and C. Hunter, “A Methodology for Testing Content-Addressable Memories,” Proc. IEEE Int'l Test Conf., pp. 471-474, 1985.
[7] C.A. Zukowski and S.-Y. Wang, “Use of Selective Precharge for Low-Power on the Match Lines of Content-Addressable Memories,” Proc. IEEE Int'l Workshop Memory, Technology, Design, and Testing, pp. 64-68, Aug. 1997.
[8] W.B. Noghani and I.P. Jalowiecki, “Yield and Cost Estimation for a CAM_Based Parallel Processor,” Proc. IEEE Int'l Workshop Memory, Technology, Design, and Testing, pp. 110-116, Aug. 1995.
[9] A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk, March LR: A Test for Realistic Linked Faults Proc. 14th VLSI Test Symp., pp. 272-280, 1996.
[10] M. Nicolaidis, V. Castro Alves, and H. Bederr, "Testing Complex Couplings in Multiport RAMs," IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 59-71, Mar. 1995.
[11] A.J. van de Goor, "Using March Tests to Test SRAMs," IEEE Design&Test of Computers, Vol. 10, No. 1, Mar. 1993, pp. 8-14.
[12] A.J. Van de Goor and G.N. Gaydadjiev, “March U: A Test for Unlinked Memory Faults,” IEEE Proc. Circuits Devices Systems, vol. 144, no. 3, June 1997.
[13] A.J. Van de Goor and I.B.S. Tlili, “Disturb Neighborhood Pattern Sensitive Fault,” IEEE Proc. VTS, pp. 37-45, Apr. 1998.
[14] W.K. Al-Assadi, A.P. Jayasumana, and Y.K. Malaiya, “On Fault Modeling and Testing of Content-Addressable Memories,” Proc. IEEE Int'l Workshop Memory, Technology, Design, and Testing, pp. 78-83, Aug. 1994.
[15] K.E. Grosspietsch, "Associative Processors and Memories: A Survey," IEEE Micro, vol. 12, no. 3, May-June 1992, pp. 12-19.

Index Terms:
Content addressable memory, memory testing, fault detection, March C algorithm, fault modeling.
J. Zhao, S. Irrinki, M. Puri, F. Lombardi, "Testing SRAM-Based Content Addressable Memories," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1054-1063, Oct. 2000, doi:10.1109/12.888041
Usage of this product signifies your acceptance of the Terms of Use.