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Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility
August 2000 (vol. 49 no. 8)
pp. 814-825

Abstract—The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling (DR) [1] is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at first-time page faults, i.e., when the code pages are accessed for the first time during execution. Treating a page of code as the unit of rescheduling makes it susceptible to the hazards of changes in the page size during the process of rescheduling. This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code. Further, it presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPs in the code. Algorithms to perform rescheduling on acyclic code and cyclic code are presented, followed by the discussion of the property of rescheduling-size invariance (RSI) satisfied by list encoding.

[1] T.M. Conte and S.W. Sathaye, “Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures,” Proc. 28th Int'l Ann. Symp. Microarchitecture, pp. 208-218, Nov. 1995.
[2] J.S. O'Donnell, “Superscalar vs. VLIW,” Computer Architecture News (ACM SIGARCH), pp. 26-28, Mar. 1995.
[3] B.R. Rau, “Dynamically Scheduled VLIW Processors,” Proc. 26th Ann. Int'l Symp. Microarchitecture, pp. 80-92, Dec. 1993.
[4] S. Melvin, M. Shebanow,, and Y. Patt, “Hardware Support for Large Atomic Units in Dynamically Scheduled Machines,” Proc. 21st Int'l Symp. Microarchitecture, pp. 60-66, Dec. 1988.
[5] G.M. Silberman and K. Ebcioglu, "An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures," Computer, June 1993, pp. 39-56.
[6] M. Franklin and M. Smotherman, "A Fill-Unit Approach to Multiple Instruction Issue," Proc. 27th Ann. Int'l Symp. Microarchitecture, pp. 162-171,San Jose, Calif., Dec. 1994.
[7] G.M. Silberman and K. Ebcioglu,"An Architectural Framework for Migration from CISC to Higher Performance Platforms," Proc. Int'l Conf. Supercomputing, pp. 198-215, 1992.
[8] B.R. Rau, D.W.L. Yen, W. Yen, and R.A. Towle, “The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs,” Computer, pp. 12-35, Jan. 1989.
[9] V. Kathail, M. Schlansker, and B.R. Rau, “HPL PlayDoh Architecture Specification: Version 1.0,” Technical Report HPL-93-80, Hewlett-Packard Laboratories, Technical Publications Dept., Palo Alto, Calif., Feb. 1994.
[10] A.E. Charlesworth, “An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family,” Computer, vol. 14, no. 9, pp. 18-27, Sept. 1981.
[11] W.W. Hwu, S.A. Mahlke, W.Y. Chen, P.P. Chang, N.J. Warter, R.A. Bringmann, R.G. Ouellette, R.E. Hank, T. Kiyohara, G.E. Haab, J.G. Holm,, and D.M. Lavery, ``The Superblock: An Effective Technique for VLIW and Superscalar Compilation,'' J. Supercomputing, vol. 7, pp. 9-50, 1993.
[12] S.A. Mahlke, D.C. Lin, W.Y. Chen, R.E. Hank, R.A. Bringmann, and W.W. Hwu, “Effective Compiler Support for Predicated Execution Using the Hyperblock,” Proc. 25th Ann. ACM/IEEE Int'l Symp. Microarchitecture, pp. 45-54, 1992.
[13] J.R. Allen,K. Kennedy,C. Porterfield,, and J. Warren,“Conversion of control dependence to data dependence,” Proc. 1983 Symp. Principles of Programming Languages, pp. 177-189, Jan. 1983.
[14] J.C.H. Park and M. Schlansker, “On Predicated Execution,” Technical Report HPL-91-58, Hewlett-Packard Laboratories, Technical Publications Dept., Palo Alto, Calif., 1991.
[15] T.M. Conte and S.W. Sathaye, “Optimization of VLIW Compatibility Systems Employing Dynamic Rescheduling,” Int'l J. Parallel Programming, accepted for publication.
[16] T.M. Conte, S.W. Sathaye, and S. Banerjia, “A Persistent Rescheduled-Page Cache for Low-Overhead Object-Code Compatibility in VLIW Architectures,” Proc. 29th Ann. Int'l Symp. Microarchitecture, Dec. 1996.
[17] M. Talluri, S. Kong, M.D. Hill, and D.A. Patterson, “Tradeoffs in Supporting Two Page Sizes,” Proc. 19th Ann. Int'l Symp. Computer Architecture (ISCA '92), pp. 415-424, May 1992.
[18] Y.A. Khalidi, M. Talluri, M.N. Nelson, and D. Williams, “Virtual Memory Support for Multiple Page Sizes,” Techical Report TR-93-17, SUN Microsystems Laboratories, Sunnyvale, Calif., 1993.
[19] M. Talluri and M.D. Hill, “Surpassing the TLB Performance of Superpages with Less Operating System Support,” Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '94), pp. 171-182, Oct. 1994.
[20] T.M. Conte, S. Banerjia, S.Y. Larin, K.N. Menezes, and S.W. Sathaye, “Instruction Cache Designs for a Class of Statically Scheduled Instruction Level Parallel Architectures,” technical report, Dept. of Electrical and Computer Eng., North Carolina State Univ., Raleigh, May 1997.
[21] T.M. Conte et al., The TINKER Machine Language Manual. Raleigh, N.C.: North Carolina State Univ. Apr. 1995.
[22] A.E. Eichenberger and E. Davidson, “A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints,” Proc. ACM SIGPLAN 1996 Conf. Programming Language Design and Implementation, May 1996.
[23] J.C. Gyllenhaal, W.W. Hwu, and B.R. Rau, “Optimization of Machine Descriptions for Efficient Use,” Proc. 29th Ann. Int'l Symp. Microarchitecture, Dec. 1996.
[24] V. Bala and N. Rubin, “Efficient Instruction Scheduling Using Finite State Automata,” Proc. 28th Ann. Int'l Symp. Microarchitecture, Nov. 1995.
[25] B.R. Rau and C.D. Glaeser,“Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientificcomputing,” Proc. 14th Ann. Workshop Microprogramming, pp. 183-198, Oct. 1981.
[26] B. Rau, C. Glaeser, and R. Picard, “Efficient Code Generation for Horizontal Architectures: Compiler Techniques and Architectural Support,” Proc. Ninth Ann. Int'l Symp. Computer Architecture, pp. 131-139, Apr. 1982.
[27] M. Lam, "Software Pipelining: An Effective Scheduling Technique for VLIW Machines," Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation, 1988.
[28] J.C. Dehner, P.Y.T. Hsu, and J.P. Bratt, "Overlapped Loop Support in the Cydra 5," Proc. ACM Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 1989.
[29] A. Nicolau and R. Potasman, “Realistic Scheduling: Compaction for Pipelined Architectures,” Proc. 23rd Ann. Int'l Symp. Microarchitecture, pp. 69-79, 1990.
[30] B. Su and J. Wang, "GURPR*: A New Global Software Pipelining Algorithm," Proc. 24th Ann. Int'l Symp. Microarchitecture (MICRO-24), pp. 212-216, Nov. 1991.
[31] B.R. Rau, M. Schlansker, and P.P. Tirumalai, “Code Generation Schemas for Modulo Scheduled DO-Loop and WHILE-Loops,” Techical Report HPL-92-47, Hewlett-Packard Laboratories, Technical Publications Dept., Palo Alto, Calif., 1992.
[32] B.R. Rau, "Iterative Modulo Scheduling: An Algorithm for Software Pipelined Loops," Proc. 27th Ann. Int'l Symp. Microarchitecture,San Jose, Calif., Dec. 1994.
[33] N. Warter, “Modulo Scheduling with Isomorphic Control Transformations,” PhD thesis, Dept. of Electrical and Computer Eng., Univ. of Illinois, Urbana-Champaign, 1994.
[34] M.G. Stoodley and C.G. Lee, “Software Pipelining Loops with Conditional Branches,” Proc. 29th Ann. Workshop Microprogramming (Micro-29), 1996,
[35] S.A. Mahlke, W.Y. Chen, R.A. Bringmann, R.E. Hank, W.W. Hwu, B.R. Rau, and M.S. Schlansker, "Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution," ACM Trans. Computer Systems, vol. 11, no. 4, pp. 376-408, Nov. 1993.

Index Terms:
Microarchitecture, processor architecture, instruction cache, VLIW, instruction-set encoding, list encoding.
Citation:
Thomas M. Conte, Sumedh Sathaye, "Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility," IEEE Transactions on Computers, vol. 49, no. 8, pp. 814-825, Aug. 2000, doi:10.1109/12.868027
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