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Location Consistency-A New Memory Model and Cache Consistency Protocol
August 2000 (vol. 49 no. 8)
pp. 798-813

Abstract—Existing memory models and cache consistency protocols assume the memory coherence property which requires that all processors observe the same ordering of write operations to the same location. In this paper, we address the problem of defining a memory model that does not rely on the memory coherence assumption and also the problem of designing a cache consistency protocol based on such a memory model. We define a new memory consistency model, called Location Consistency (LC), in which the state of a memory location is modeled as a partially ordered multiset (pomset) of write and synchronization operations. We prove that LC is strictly weaker than existing memory models, but is still equivalent to stronger models for the common case of parallel programs that have no data races. We also describe a new multiprocessor cache consistency protocol based on the LC memory model. We prove that this LC protocol obeys the LC memory model. The LC protocol does not need to enforce single write ownership of memory blocks. As a result, the LC protocol is simpler and more scalable than existing snooping and directory-based cache consistency protocols.

[1] S.V. Adve and M.D. Hill,“A unified formalization of four shared-memory models,” IEEE Trans. on Parallel and Distributed Systems, vol. 4, no. 6, pp. 613-624, June 1993.
[2] B. Bershad, M. Zekauskas, and W. Sawdon, "The Midway Distributed Shared Memory System," Digest of Papers, COMPCON Spring '93 [Proc. 38th IEEE Computer Soc. Int'l Computer Conf.], IEEE Computer Soc. Press, Los Alamitos, Calif., 1993, pp. 528-537.
[3] R.D. Blumofe, M. Frigo, C.F. Joerg, C.E. Leiserson, and K.H. Randall, “An Analysis of Dag-Consistent Distributed Shared-Memory Algorithms,” Proc. Eighth Ann. ACM Symp. Parallel Algorithms and Architectures, pp. 297-308, June 1996.
[4] P.B. Hansen, “The Programming Language Concurrent Pascal,” IEEE Trans. Software Eng., vol. 1, no. 2, pp. 199-206, June 1975.
[5] J.B. Carter, J.K. Bennett, and W. Zwaenepoel, "Implementation and Performance of Munin," Proc. 13th ACM SIGOPS Symp. Operating Systems Principles, pp. 152-164,Pacific Grove, Calif., Oct. 1991.
[6] D.E. Culler and J.P. Singh, Parallel Computer Architecture. first ed. Morgan Kaufmann, 1999.
[7] F. Darema, D.A. George, V.A. Norton, and G.F. Pfister, “A Single-Program-Multiple-Data Computational Model for EPEX/FORTRAN,” Parallel Computing, vol. 7, pp. 11-24, Apr. 1988.
[8] Java in a Nutshell, Paula Ferguson, ed. Sebastopol, Calif.: O'Reilly&Associates, 1996.
[9] J. Ferrante,K.J. Ottenstein,, and J.D. Warren,“The program dependence graph and its use in optimization,” ACM Trans. Programming Languages and Systems, vol. 9, no. 3, pp. 319-349, June 1987.
[10] M. Frigo, “The Weakest Reasonable Memory Model,” master's thesis, Massachusetts Inst. of Tech nology, 1998.
[11] G.R. Gao and V. Sarkar, “Location Consistency: Stepping beyond the Barriers of Memory Coherence and Serializability,” ACAPS Technical Memo 78, School of Computer Science, McGill Univ., Montréal, Québec, Canada, Dec. 1993, revised Dec. 1994.
[12] G.R. Gao and V. Sarkar, “Location Consistency: Stepping beyond Memory Coherence Barrier,” Proc. 1995 Int'l Conf. Parallel Processing, vol. II, pp. 73-76, Aug. 1995.
[13] G.R. Gao and V. Sarkar, “On the Importance of an End-to-End View of Memory Consistency in Future Computer Systems,” Proc. Int'l Symp. High Performance Computing, pp. 30-41, 1997.
[14] K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy, “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors,” Proc. 17th Ann. Int'l Symp. Computer Architecture, 1990.
[15] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[16] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1995.
[17] A.H. Karp and V. Sarkar, “Data Merging for Shared-Memory Multiprocessors,” Proc. 26th Hawaii Int'l Conf. System Sciences, Volume I (Architecture), pp. 244-256, Jan. 1993.
[18] P. Keleher, A.L. Cox, and W. Zwaenepoel, “Lazy Release Consistency for Software Distributed Shared Memory,” Proc. 19th Ann. Int'l Symp. Computer Architecture, pp. 13-21, May 1992.
[19] L. Lamport, “How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs,” IEEE Trans. Computers, vol. 28, no. 9, pp. 690-691, Sept. 1979.
[20] D. Lenoski, K. Gharachorloo, J. Laudon, A. Gupta, J. Hennessy, M. Horowitz, and M. Lam, “Design of Scalable Shared-Memory Multiprocessors: The DASH Approach,” Digest of Papers, 35th IEEE Computer Society Int'l Conf., COMPCON Spring '90, pp. 62-67, Feb.-Mar. 1990.
[21] S. Merali, “Designing and Implementing Memory Consistency Models for Shared-Memory Multiprocessors,” master's thesis, McGill Univ., Montréal, Québec, Canada, Apr. 1996.
[22] W. Pugh, “The Java Memory Model,” , 1999.
[23] V. Sarkar, “A Concurrent Execution Semantics for Parallel Program Graphs and Program Dependence Graphs,” Proc. Fifth Int'l Workshop Languages and Compilers for Parallel Computing, pp. 16-30, Aug. 1992.
[24] A.C. Shaw, The Logical Design of Operating Systems. Prentice Hall, 1974.
[25] P. Tang and P.-C. Yew, “Processor Self-Scheduling for Multiple-Nested Parallel Loops,” Proc. 1986 Int'l Conf. Parallel Processing, Feb. 1986.

Index Terms:
Memory consistency, location consistency, cache consistency protocols.
Guang R. Gao, Vivek Sarkar, "Location Consistency-A New Memory Model and Cache Consistency Protocol," IEEE Transactions on Computers, vol. 49, no. 8, pp. 798-813, Aug. 2000, doi:10.1109/12.868026
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