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Chichyang Chen, RuiLin Chen, ChihHuan Yang, "Pipelined Computation of Very Large WordLength LNS Addition/Subtraction with Polynomial Hardware Cost," IEEE Transactions on Computers, vol. 49, no. 7, pp. 716726, July, 2000.  
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@article{ 10.1109/12.863041, author = {Chichyang Chen and RuiLin Chen and ChihHuan Yang}, title = {Pipelined Computation of Very Large WordLength LNS Addition/Subtraction with Polynomial Hardware Cost}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {7}, issn = {00189340}, year = {2000}, pages = {716726}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.863041}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Pipelined Computation of Very Large WordLength LNS Addition/Subtraction with Polynomial Hardware Cost IS  7 SN  00189340 SP716 EP726 EPD  716726 A1  Chichyang Chen, A1  RuiLin Chen, A1  ChihHuan Yang, PY  2000 KW  Logarithmic arithmetic KW  logarithmic number system KW  exponentials KW  logarithms KW  digit online algorithms KW  pipelined architecture. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—A novel pipelined method is proposed to compute the addition/subtraction in very large wordlength logarithmic number system (LNS) arithmetic. Digitparallel additivenormalization and digit online multiplicativenormalization methods are adopted to compute the exponential and logarithmic functions, respectively, in LNS addition/subtraction. These two methods can both be implemented in a pipelined and regular architecture. The size of the required lookup tables is now proportional to a thirdorder polynomial function, instead of an exponential function, of the word length. The total size of the tables in a 32bit LNS unit is estimated to be less than 53.5 kbits and the total size of the tables in a 64bit LNS unit will be less than 471 kbits. Furthermore, the hardware cost of the other circuits in the proposed LNS unit is only proportional to the square of the word length. This study also develops a simple leadingzerobits prediction technique that can significantly enhance the precision in LNS addition/subtraction computation. When compared to floatingpoint arithmetic design, our approach still suffers from large hardware cost and pipeline latency. However, the proposed approach has provided a theoretical advancement in the development of very large wordlength LNS arithmetic.
[1] G.L. Sicuranza, “On Efficient Implementations of 2D Digital Filters Using Logarithmic Number System,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 31, pp. 877885, 1983.
[2] E.E. Swartzlander Jr., D.V.S. Chandra, H.T. Nagle Jr., and S.A. Starks, “Sign/Logarithm Arithmetic for FFT Implementation,” IEEE Trans. Computers, vol. 32, no. 6, pp. 526534, June 1983.
[3] D. Das, K. Mukhopadhyaya, and B.P. Sinha, “Implementation of Four Common Functions on an LNS CoProcessor,” IEEE Trans. Computers, vol. 44, no. 1, pp. 155161, Jan. 1995.
[4] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[5] M.L. Frey and F.J. Taylor, “A Table Reduction Technique for Logarithmically Architected Digital Filters,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 33, no. 3, pp. 718719, June 1985.
[6] D.M. Lewis, "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System," IEEE Trans. Computers, pp. 1,3251,336, 1990.
[7] L.K. Yu and D.M. Lewis, “A 30b Integrated Logarithmic Number System Processor,” IEEE J. SolidState Circuits, vol. 26, pp. 1,4331,440, Oct. 1991.
[8] D.M. Lewis, "Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit," IEEE Trans. Computers, Aug. 1994, pp. 974982.
[9] H. Henkel, “Improved Addition for Logarithmic Number System,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 37, no. 2, pp. 301303, Feb. 1989.
[10] J.N. Coleman and E.I. Chester, “A 32Bit Logarithmic Arithmetic Unit and Its Performance Compared to FloatingPoint,” Proc. 14th IEEE Symp. Computer Arithmetic, pp. 142151, 1999.
[11] M.G. Arnold, T.A. Bailey, J.R. Cowles, and J.J. Cupal, "Redundant Logarithmic Arithmetic," IEEE Trans. Computers, vol. 39, no. 8, pp. 1,0771,086, Aug. 1990.
[12] J.M. Muller, A. Scherbyna, and A. Tisserand, “SemiLogarithmic Number Systems,” IEEE Trans. Computers, vol. 47, no. 2, pp. 145151, Feb. 1998.
[13] F. Lai and C.F.E. Wu, “A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities,” IEEE Trans. Computers, vol. 40, no. 8, pp. 952962, Aug. 1991.
[14] T.C. Chen, “Automatic Computation of Exponentials, Logarithms, Ratios, and Square Roots,” IBM J. Research and Development, vol. 16, pp. 380388, July 1972.
[15] R.M. Owens and M.J. Irwin, “OnLine Algorithms for the Design of Pipeline Architectures,” Proc. Conf. Computer Arithmetic, pp. 1219, 1979.
[16] C. Chen and C.H. Yang, “Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables,” Proc. Int'l Conf. Computer Design, pp. 292297, Oct. 1998.
[17] H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi, “LeadingZero Anticipatory Logic for High Speed Floating Point Addition,” IEEE J. SolidState Circuits, vol. 31, no. 8, pp. 1,1571,164, 1996.
[18] S. Muroga, VLSI System Design: When and How to Design VeryLargeScale Integrated Circuits. New York: Wiley, 1982.
[19] D. Lewis, “Complex Logarithmic Number System Arithmetic Using HighRadix Redundant CORDIC Algorithms,” Proc. 14th IEEE Symp. Computer Arithmetic, pp. 194203, 1999.