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Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost
July 2000 (vol. 49 no. 7)
pp. 716-726

Abstract—A novel pipelined method is proposed to compute the addition/subtraction in very large word-length logarithmic number system (LNS) arithmetic. Digit-parallel additive-normalization and digit on-line multiplicative-normalization methods are adopted to compute the exponential and logarithmic functions, respectively, in LNS addition/subtraction. These two methods can both be implemented in a pipelined and regular architecture. The size of the required lookup tables is now proportional to a third-order polynomial function, instead of an exponential function, of the word length. The total size of the tables in a 32-bit LNS unit is estimated to be less than 53.5 kbits and the total size of the tables in a 64-bit LNS unit will be less than 471 kbits. Furthermore, the hardware cost of the other circuits in the proposed LNS unit is only proportional to the square of the word length. This study also develops a simple leading-zero-bits prediction technique that can significantly enhance the precision in LNS addition/subtraction computation. When compared to floating-point arithmetic design, our approach still suffers from large hardware cost and pipeline latency. However, the proposed approach has provided a theoretical advancement in the development of very large word-length LNS arithmetic.

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Index Terms:
Logarithmic arithmetic, logarithmic number system, exponentials, logarithms, digit on-line algorithms, pipelined architecture.
Citation:
Chichyang Chen, Rui-Lin Chen, Chih-Huan Yang, "Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost," IEEE Transactions on Computers, vol. 49, no. 7, pp. 716-726, July 2000, doi:10.1109/12.863041
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