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J.n. Coleman, E.i. Chester, C.i. Softley, J. Kadlec, "Arithmetic on the European Logarithmic Microprocessor," IEEE Transactions on Computers, vol. 49, no. 7, pp. 702715, July, 2000.  
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@article{ 10.1109/12.863040, author = {J.n. Coleman and E.i. Chester and C.i. Softley and J. Kadlec}, title = {Arithmetic on the European Logarithmic Microprocessor}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {7}, issn = {00189340}, year = {2000}, pages = {702715}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.863040}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Arithmetic on the European Logarithmic Microprocessor IS  7 SN  00189340 SP702 EP715 EPD  702715 A1  J.n. Coleman, A1  E.i. Chester, A1  C.i. Softley, A1  J. Kadlec, PY  2000 KW  Digital arithmetic KW  logarithmic number system KW  interpolation. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—A new European research project aims to develop a microprocessor based on the logarithmic number system, in which a real number is represented as a fixedpoint logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage over floatingpoint if addition and subtraction can be performed with speed and accuracy at least equal to that of floatingpoint, but these operations require the interpolation of a nonlinear function which has hitherto been either timeconsuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately and show that these operations are thereby competitive with their floatingpoint equivalents. We then present some largescale case studies which show that the average performance of the LNS exceeds floatingpoint, in terms of both speed and accuracy.
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