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High-Speed Booth Encoded Parallel Multiplier Design
July 2000 (vol. 49 no. 7)
pp. 692-701

Abstract—This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.

[1] A.D. Booth, “A Signed Binary Multiplication Technique,” Quarterly J. Mechanical and Applied Math., vol. 4, pp. 236-240, 1951.
[2] O.L. MacSorley, “High Speed Arithmetic in Binary Computers,” Proc. IRE, vol. 49, pp. 67-91, 1961.
[3] D. Villeger and V.G. Oklobdzija, “Analysis of Booth Encoding Efficiency in Parallel Multipliers Using Compressors for Reduction of Partial Products,” Proc. IEEE 27th Asilomar Conf. Signals, Systems, and Computer, vol. 1, pp. 781-784, 1993.
[4] D. Villeger and V.G. Oklobdzija, “Evaluation of Booth Encoding Techniques for Parallel Multiplier Implementation,” Electronics Letters, vol. 29, no. 23, pp. 2,016-2,017, Nov. 1993.
[5] C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Computers, vol. 13, no. 2, pp. 14-17, Feb. 1964.
[6] L. Dadda, “Some Schemes for Parallel Multiplier,” Alta Frequenza, vol. 34, pp. 349-356, Mar. 1965.
[7] A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bulletin, vol. 23, Jan. 1981.
[8] M. Nagamatsu et al., “A 15 ns$32\times32$-bit CMOS Multiplier with an Improved Parallel Structure,” Digest of Technical Papers, IEEE Custom Integrated Circuits Conf., 1989.
[9] P. Song and G. De Micheli, “Circuit and Architecture Trade-Offs for High-Speed Multiplication,” IEEE J. Solid State Circuits, vol. 26, no. 9, Sept. 1991.
[10] D. Zuras and W.H. McAllister, “Balanced Delay Trees and Combinatorial Division in VLSI,” IEEE J. Solid-State Circuits, vol. 21, pp. 814-819, Oct. 1986.
[11] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[12] V.G. Oklobdzija, D. Villeger, and S.S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Trans. Computers, vol. 45, no. 3, pp. 294-305, Mar. 1996.
[13] P.F. Stelling, C.U. Martel, V.G. Oklobdzija, and R. Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Trans. Computers, vol. 47, no. 3, pp. 273-285, Mar. 1998.
[14] M.D. Ercegovac et al., Fast Multiplication without Carry-Propagate Addition , IEEE Trans. Computers, vol. 39, no. 11, Nov. 1990.
[15] R.K. Kolagotla et al., VLSI Implementation of a 200-Mhz 16$\times$16 Left-to-Right Carry-Free Multiplier in 0.35$\mu \rm m$CMOS Technology for Next-Generation DSPs , Proc. IEEE 1997 Custom Integrated Circuits Conf., pp. 469-472, 1997.
[16] P.F. Stelling and V.G. Oklobdzija, “Optimal Designs for Multipliers and Multiply-Accumulators,” Proc. 15th IMACS World Congress Scientific Computation, Modeling, and Applied Math., A. Sydow, ed., pp. 739-744, Aug. 1997.
[17] Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corporation, Mar. 1998.
[18] G. Goto et al., “A 4.1ns compact$54\times54$-b Multiplier Utilizing Sign-Select Booth Encoders,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1,676-1,682, Nov. 1997.
[19] G. Goto et al., “A$54\times54$-b Regularly Structured Tree Multiplier,” IEEE J. Solid-State Circuits, vol. 27, no. 9, Sept. 1992.
[20] R. Fried, “Minimizing Energy Dissipation in High-Speed Multipliers,” Proc. 1997 Int'l Symp. Low Power Electronics and Design, pp. 214-219, 1997.
[21] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.
[22] J. Fadavi-Ardekani, "M×N Booth Encoded Multiplier Generator Using Optimized Wallace Trees," IEEE Trans. VLSI Systems, June 1993, pp. 120-125.
[23] A.A. Farooqui et al., “General Data-Path Organization of a MAC Unit for VLSI Implementation of DSP Processors,” Proc. 1998 IEEE Int'l Symp. Circuits and Systems, vol. 2, pp. 260-263, 1998.
[24] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[25] K.-H Cheng, S.-M. Chiang, and S.-W. Cheng, The Improvement of Conditional Sum Adder for Low Power Applications Proc. 11th Ann. IEEE Int'l Application Specific Integrated Circuits Conf., pp. 131-134, 1998.

Index Terms:
Final adder, Booth encoding, multiple-level conditional-sum adder, and parallel multiplier.
Wen-Chang Yeh, Chein-Wei Jen, "High-Speed Booth Encoded Parallel Multiplier Design," IEEE Transactions on Computers, vol. 49, no. 7, pp. 692-701, July 2000, doi:10.1109/12.863039
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