Issue No.07 - July (2000 vol.49)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.863039
<p><b>Abstract</b>—This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.</p>
Final adder, Booth encoding, multiple-level conditional-sum adder, and parallel multiplier.
Wen-Chang Yeh, Chein-Wei Jen, "High-Speed Booth Encoded Parallel Multiplier Design", IEEE Transactions on Computers, vol.49, no. 7, pp. 692-701, July 2000, doi:10.1109/12.863039