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| Wen-Chang Yeh, Chein-Wei Jen, "High-Speed Booth Encoded Parallel Multiplier Design," IEEE Transactions on Computers, vol. 49, no. 7, pp. 692-701, July, 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/12.863039, author = {Wen-Chang Yeh and Chein-Wei Jen}, title = {High-Speed Booth Encoded Parallel Multiplier Design}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {7}, issn = {0018-9340}, year = {2000}, pages = {692-701}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.863039}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - High-Speed Booth Encoded Parallel Multiplier Design IS - 7 SN - 0018-9340 SP692 EP701 EPD - 692-701 A1 - Wen-Chang Yeh, A1 - Chein-Wei Jen, PY - 2000 KW - Final adder KW - Booth encoding KW - multiple-level conditional-sum adder KW - and parallel multiplier. VL - 49 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.
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