This Article 
 Bibliographic References 
 Add to: 
Integer Multiplication with Overflow Detection or Saturation
July 2000 (vol. 49 no. 7)
pp. 681-691

Abstract—High-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two $n$-bit integers are multiplied to produce a $2n$-bit product. To prevent growth in word length, processors typically return the $n$ least significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation. These methods have significantly less area and delay than conventional methods for integer multiplication with overflow detection or saturation.

[1] D. Tabak, RISC Systems and Applications. John Wiley&Sons, 1996.
[2] J.C. Hoffman and R. Kitai, “Parallel Multiplier Circuit,” Electronic Letters, vol. 4, p. 178, May 1968.
[3] S.D. Pezaris, “A 40 ns 17-bit Array Multiplier,” IEEE Trans. Computers, vol. 20, no. 4, pp. 442-447, Apr. 1971.
[4] K.Z. Pekmestzi, “Multiplexer-Based Array Multipliers,” IEEE Trans. Computers, vol. 48, no. 1, pp. 15-23, Jan. 1999.
[5] C.S. Wallace, “Suggestion for a Fast Multiplier,” IEEE Trans. Electronic Computers, vol. 13, pp. 14-17, 1964.
[6] L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-356, 1965.
[7] K.C. Bickerstaff, M.J. Schulte, and E.E. SwartzlanderJr., “Parallel Reduced Area Multipliers,” J. VLSI Signal Processing, pp. 181-191, Apr. 1995.
[8] P. Song and G. De Micheli, “Circuit and Architecture Trade-Offs for High-Speed Multiplication,” IEEE J. Solid State Circuits, vol. 26, no. 9, Sept. 1991.
[9] I. Koren, Computer Arithmetic and Algorithms. Brookside Court Publishers, 1998.
[10] T. Lindholm and F. Yellin, The Java Virtual Machine Specification, Addison-Wesley, Reading, Mass., 1997.
[11] K. Guttag, “Built-In Overflow Detection Speeds 16-bit Microprocessor Arithmetic,” EDN, vol. 28, no. 1, pp. 133-135, Jan. 1983.
[12] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1995.
[13] P. Lapsley, DSP Processor Fundamentals: Architectures and Features. IEEE Press, 1997.
[14] N. Yadav, M.J. Schulte, and J. Glossner, “Parallel Saturating Fractional Arithmetic Units,” Proc. Ninth Great Lakes Symp. VLSI, pp. 214-217, Mar. 1999.
[15] F. Mintzer and A. Peled, “A Microprocessor for Signal Processing, the RSP,” IBM J. Research and Development, vol. 26, no. 4, pp. 413-423, July 1982.
[16] A. Peleg and U. Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro, vol. 16, no. 4, pp. 42-50, Aug. 1996.
[17] A. Landauro and J. Lienard, “On Overflow Detection and Correction in Digital Filters,” IEEE Trans. Computers, vol. 24, no. 12, pp. 1,226-1,228, Dec. 1975.
[18] P.D. Pai and A. Tran, “Overflow Detection in Multioperand Addition,” Int'l J. Electronics, vol. 73, no. 3, pp. 461-469, Sept. 1992.
[19] D.G. East and J.W. Moore, “Overflow Indication in Two's Complement Arithmetic,” IBM Technical Disclosure Bulletin, vol. 19, no. 8, pp. 3,135-3,136, Jan. 1977.
[20] Z. Wang, G.A. Jullien, and W.C. Miller, “A New Design Technique for Column Compression Multipliers,” IEEE Trans. Computers, vol. 44, no. 8, pp. 962-970, Aug. 1995.
[21] V.G. Oklobdzija and D. Villeger, "Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology," IEEE Trans. VLSI Systems, vol. 3, no. 2, pp. 292-301, June 1995.
[22] C.R. Baugh and B.A. Wooley, “A Two's Complement Parallel Array Multiplication Algorithm,” IEEE Trans. Computers, vol. 22, no. 12, pp. 1,045-1,047, Dec. 1973.
[23] P.E. Blankenship, “Comments on a Two's Complement Parallel Array Multiplication Algorithm,” IEEE Trans. Computers, vol. 23, p. 1,327 1974.
[24] J.A. Gibson and R.W. Gibbard, “Synthesis and Comparison of Two's Complement Parallel Multipliers,” IEEE Trans. Computers, vol. 24, no. 10, pp. 1,020-1,027, Oct. 1975.
[25] A.D. Booth, “A Signed Binary Multiplication Technique,” Quarterly J. Mechanics and Applied Mathematics, vol. 4, pp. 236-240, 1951.
[26] H. Sam and A. Gupta, “A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations,” IEEE Trans. Computers, vol. 39, no. 8, pp. 1,006-1,015, Aug. 1990.
[27] R. De Mori and A. Serra, “A Parallel Structure for Signed-Number Multiplication and Addition,” IEEE Trans. Computers, vol. 21, no. 12, pp. 1,453-1,454, Dec. 1972.
[28] M. Zheng and A. Albicki, “Low Power and High Speed Multiplication Design through Mixed Number Representations,” Proc. Int'l Conf. Computer Design, pp. 566-570, 1995.

Index Terms:
Overflow, saturation, two's complement, unsigned, integer, array multipliers, tree multipliers, computer arithmetic.
Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato, "Integer Multiplication with Overflow Detection or Saturation," IEEE Transactions on Computers, vol. 49, no. 7, pp. 681-691, July 2000, doi:10.1109/12.863038
Usage of this product signifies your acceptance of the Terms of Use.