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High-Speed Parallel-Prefix Modulo 2n - 1 Adders
July 2000 (vol. 49 no. 7)
pp. 673-680

Abstract—A novel parallel-prefix architecture for high speed modulo 2n-1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.

[1] M.A. Soderstrand,W.K. Jenkins,G.A. Jullien,, and F.J. Taylor,Residue Number System Arithmetic: Modern Applicationsin Digital Signal Processing. IEEE Press, 1986.
[2] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[3] K. Elleithy and M. Bayoumi, “Fast and Flexible Architectures for RNS Arithmetic Decoding,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 226-235, Apr. 1992.
[4] M.A. Bayoumi, G.A. Jullien, and W.C. Miller, “A Look-Up Table VLSI Design Methodology for RNS Structures Used in DSP Applications,” IEEE Trans. Circuits and Systems, vol. 34, pp. 604-616, June 1987.
[5] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[6] B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, pp. 394-402. Reading, Mass.: Addison-Wesley, June 1989.
[7] T.R.N. Rao, Error Coding for Arithmetic Processors.New York: Academic Press, 1974.
[8] D. Nikolos, A. Paschalis, and G. Philokyprou, "Efficient Design of Totally Self-Checking Checkers for Low-Cost Arithmetic Codes," IEEE Trans. Computers, vol. 38, no. 7, pp. 807-814, July 1988.
[9] I.L. Sayers and D.J. Kinniment, “Low-Cost Residue Codes and Their Application to Self-Checking VLSI Systems,” IEE Proc. Computers and Digital Techniques, vol. 132, no. 4, pp. 197-202, 1985.
[10] R. Zimmermann et al., A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm IEEE} J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, 1994.
[11] A. Curiger, “VLSI Architectures for Computations in Finite Rings and Fields,” PhD thesis, Swiss Federal Inst. of Technology (ETH), Zurich, 1993.
[12] R. Zimmerman, Efficient VLSI Implementation of Modulo$(2^n\pm 1)$Addition and Multiplication Proc. 14th IEEE Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
[13] A. Tyagi, A Reduced-Area Scheme for Carry-Select Adders IEEE Trans. Computers, vol. 42, no. 10, Oct. 1993.
[14] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[15] R.E. Ladner and M.J. Fischer, "Parallel Prefix Computation," J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[16] R.P. Brent and H.T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.
[17] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. 22, no. 8, pp. 783-791, Aug. 1973.
[18] J. Sklansky, “Conditional Sum Addition Logic,” IRE Trans. Electronic Computers, vol. 9, no. 6, pp. 226-231, June 1960.
[19] R. Zimmermann, “Binary Adder Architectures for Cell-Based VLSI and Their Synthesis,” PhD thesis, Swiss Federal Inst. of Technology, Zurich, 1997 (available at
[20] J.J. Shedletsky, “Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder,” IEEE Trans. Computers, vol. 26, pp. 271-272, Mar. 1977.
[21] J.F. Wakerly, “One's Complement Adder Eliminates Unwanted Zero,” Electronics, pp. 103-105, Feb. 1976.
[22] C. Efstathiou, D. Nikolos, and J. Kalamatianos, Area-Time Efficient Modulo$2^n-1$Adder Design IEEE Trans. Circuits and Systems II, vol. 41, no. 7, pp. 463-467, 1994.
[23] M. Bayoumi and G. Jullien, A VLSI Implementation of Residue Adders IEEE Trans. Circuits Systems, vol. 34, pp. 284-288, 1987.
[24] Design Analyzer Tools Suite, version 1998.08, Synopsys Inc.

Index Terms:
Modulo $2^n-1$ adders, parallel-prefix adders, carry look-ahead adders, VLSI design.
Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos, "High-Speed Parallel-Prefix Modulo 2n - 1 Adders," IEEE Transactions on Computers, vol. 49, no. 7, pp. 673-680, July 2000, doi:10.1109/12.863036
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