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High-Speed Parallel-Prefix Modulo 2n - 1 Adders
July 2000 (vol. 49 no. 7)
pp. 673-680

Abstract—A novel parallel-prefix architecture for high speed modulo 2n-1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.

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Index Terms:
Modulo $2^n-1$ adders, parallel-prefix adders, carry look-ahead adders, VLSI design.
Citation:
Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos, "High-Speed Parallel-Prefix Modulo 2n - 1 Adders," IEEE Transactions on Computers, vol. 49, no. 7, pp. 673-680, July 2000, doi:10.1109/12.863036
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