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Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
June 2000 (vol. 49 no. 6)
pp. 596-607

Abstract—We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by-product, the fault coverage is sometimes increased as well. Additionally, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vectors are not generated.

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Index Terms:
Static test compaction, synchronous sequential circuits, test application time.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 49, no. 6, pp. 596-607, June 2000, doi:10.1109/12.862219
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