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Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR
June 2000 (vol. 49 no. 6)
pp. 588-595

Abstract—Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt's algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided into thirds, and the rest of the divider logic replicated around each part, to provide three independent dividers. While this reduces the size of the fault-tolerant dividers over that of traditional TMR, latency may be increased. However, both division algorithms can be modified to use lower precision multiplications during the early iterations. This saves multiply cycles and, hence, produces a faster divider.

[1] B.W. Johnson, J.H. Aylor, and H.H. Hana, “Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection in a 32-bit VLSI Adder,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 208-215, Feb. 1988.
[2] Y.-M. Hsu and E.E. SwartzlanderJr., “VLSI Concurrent Error Correcting Adders and Multipliers,” Proc. 1993 IEEE Int'l Workshop Defect and Fault Tolerance in VLSI Systems, pp. 287-294, Nov. 1993.
[3] A. Antola, R. Negrini, M.G. Sami, and N. Scarabottolo, “Fault Tolerance in FFT Arrays: Time Redundancy Approaches,” J. VLSI Signal Processing, vol. 4, no. 4, pp. 295-316, Nov. 1992.
[4] S.F. Oberman and M.J. Flynn, “Division Algorithms and Implementations,” IEEE Trans. Computers, vol. 46, no. 8, pp. 833-854, Aug. 1997.
[5] M.J. Flynn, “On Division by Functional Iteration,” IEEE Trans. Computers, vol. 19, no. 8, pp. 702-706, Aug. 1970.
[6] S.F. Anderson, J.G. Earle, R.E. Goldschmidt, and D.M. Powers, “The IBM System/360 Model 91: Floating-Point Execution Unit,” IBM J. Research and Development, vol. 11, pp. 34-53, Jan. 1967.
[7] S.F. Oberman and M.J. Flynn, “Fast IEEE Rounding for Division by Functional Iteration,” Technical Report CSL-TR-96-700, Stanford Univ., July 1996.
[8] W.L. Gallagher and E.E. SwartzlanderJr., “Power Consumption in Fast Dividers Using Time Shared TMR,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 256-264, Nov. 1999.
[9] B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, pp. 394-402. Reading, Mass.: Addison-Wesley, June 1989.
[10] P. Montuschi, L. Ciminiera, and A. Guistina, “Division Unit with Newton-Raphson Approximation and Digit-by-Digit Refinement of the Quotient,” IEE Proc.: Computers and Digital Techniques, vol. 141, no. 6, pp. 317-324, Nov. 1994.
[11] LSI Logic 1.0 Micron Cell-Based Products Databook, LSI Logic Corporation, Milpitas, Calif., Feb. 1991.
[12] K.C. Bickerstaff, M.J. Schulte, and E.E. SwartzlanderJr., “Parallel Reduced Area Multipliers,” J. VLSI Signal Processing, pp. 181-191, Apr. 1995.

Index Terms:
Division, fault-tolerant arithmetic, Newton-Raphson division, Goldschmidt division, time shared TMR.
W. Lynn Gallagher, Earl E. Swartzlander, "Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR," IEEE Transactions on Computers, vol. 49, no. 6, pp. 588-595, June 2000, doi:10.1109/12.862218
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